[PATCH v2 2/2] clk: mediatek: add infracfg reset controller for mt7988

[AngeloGioacchino Del Regno]

Il 05/01/24 17:20, Frank Wunderlich ha scritto:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> Infracfg can also operate as reset controller, add support for it.
> 
> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> ---
>   drivers/clk/mediatek/clk-mt7988-infracfg.c | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c
> index 8011ef278bea..1660a45349ff 100644
> --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
> +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
> @@ -14,6 +14,9 @@
>   #include "clk-gate.h"
>   #include "clk-mux.h"
>   #include <dt-bindings/clock/mediatek,mt7988-clk.h>
> +#include <dt-bindings/reset/mediatek,mt7988-resets.h>
> +
> +#define	INFRA_RST_SET_OFFSET	0x80
>   
>   static DEFINE_SPINLOCK(mt7988_clk_lock);
>   
> @@ -249,12 +252,29 @@ static const struct mtk_gate infra_clks[] = {
>   	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
>   };
>   
> +static u16 infra_rst_ofs[] = {
> +	INFRA_RST_SET_OFFSET,
> +};
> +
> +static u16 infra_idx_map[] = {
> +	[MT7988_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 9,

The MT7988A datasheet says that INFRA_RST0 bit 9 is CONN2EMI_M0_GALS_SLV_SWRST, so
this is wrong: THERM_CTRL_SWRST is in the RST1 register, bit 9.

Also, I'm sure that you really want to add the PCIe MAC reset bit as well, to be
used with the PCIe driver...

[MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
[MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,

Enjoy... :-)

Cheers,
Angelo