[PATCH v2 4/5] arm: dts: mt7623: mux phy0 on Bananapi BPI-R2

[Arınç ÜNAL]

OK, hold this patch series, I'm going to send v3 soon with enabling both 
CPU ports to support changing the DSA master. We've got developments on 
the MediaTek ethernet driver and MT7530 DSA subdriver that surpassed my 
expectations.

Arınç

On 1.02.2023 21:56, arinc9.unal at gmail.com wrote:
> From: Arınç ÜNAL <arinc.unal at arinc9.com>
> 
> Mux the MT7530 switch's phy0 to gmac5 which is wired to the SoC's gmac1.
> This achieves 2 Gbps total bandwidth to the CPU using the second RGMII.
> 
> With this, the interface name to access phy0 changes from wan to eth1.
> 
> Signed-off-by: Arınç ÜNAL <arinc.unal at arinc9.com>
> ---
>   arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 15 ++++++++++-----
>   1 file changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> index dc9b4f99eb8b..64700253fd35 100644
> --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> @@ -182,6 +182,12 @@ fixed-link {
>   	};
>   };
>   
> +&gmac1 {
> +	status = "okay";
> +	phy-mode = "rgmii";
> +	phy-handle = <&ethphy0>;
> +};
> +
>   &eth {
>   	status = "okay";
>   
> @@ -189,6 +195,10 @@ mdio-bus {
>   		#address-cells = <1>;
>   		#size-cells = <0>;
>   
> +		ethphy0: ethernet-phy at 0 {
> +			reg = <0>;
> +		};
> +
>   		switch at 1f {
>   			compatible = "mediatek,mt7530";
>   			reg = <0x1f>;
> @@ -200,11 +210,6 @@ ports {
>   				#address-cells = <1>;
>   				#size-cells = <0>;
>   
> -				port at 0 {
> -					reg = <0>;
> -					label = "wan";
> -				};
> -
>   				port at 1 {
>   					reg = <1>;
>   					label = "lan0";