[PATCH v1 3/5] arm64: dts: mt8195: add gce node

[jason-jh.lin]

add gce node on dts file.

Change-Id: I805455cb7c645cb5a24ce1c87fe891a807069123
Signed-off-by: jason-jh.lin <jason-jh.lin at mediatek.com>
---
This patch is based on [1]
[1] Add Mediatek SoC MT8195 and evaluation board dts and Makefile
    - https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index c146a91c6272..38054196eea4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/gce/mt8195-gce.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/power/mt8195-power.h>
@@ -717,6 +718,26 @@
 			#clock-cells = <1>;
 		};
 
+		gce0: mdp_mailbox at 10320000 {
+			compatible = "mediatek,mt8195-gce";
+			reg = <0 0x10320000 0 0x4000>;
+			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
+			#mbox-cells = <3>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
+				 <&infracfg_ao CLK_INFRA_AO_GCE2>;
+			clock-names = "gce", "gce1";
+		};
+
+		gce1: disp_mailbox at 10330000 {
+			compatible = "mediatek,mt8195-gce";
+			reg = <0 0x10330000 0 0x4000>;
+			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
+			#mbox-cells = <3>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
+				 <&infracfg_ao CLK_INFRA_AO_GCE2>;
+			clock-names = "gce", "gce1";
+		};
+
 		uart0: serial at 11001100 {
 			compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
 			reg = <0 0x11001100 0 0x100>;
-- 
2.18.0