[PATCH 8/8] arm64: dts: renesas: r9a08g046: Add I3C support

[Diogo Ivo]

Add the I3C Bus Interface node to the RZ/G3L (R9A08G046) SoC DTSI and
enable it on the RZ/G3L SMARC EVK, together with the required pin
control.

The I3C pins are shared with RIIC3, so the controller is only enabled
when the SW_I3C_EN switch is on.

The I3C I/O voltage can be set to 1.2V or 1.8V on the board through
the SYS.3 (I3C_IOVS) switch, so configure the pin controller for the
selected voltage through the power-source property.

Signed-off-by: Diogo Ivo <diogo.ivo.sx at renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi         | 35 ++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts | 21 +++++++++++++
 arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi   |  4 +++
 3 files changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index f33d5d7468ff..1b0b95b12ef8 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -620,6 +620,41 @@ canfd: can at 100c0000 {
 			/* placeholder */
 		};
 
+		i3c: i3c at 100e0000 {
+			compatible = "renesas,r9a08g046-i3c";
+			reg = <0 0x100e0000 0 0x1000>;
+			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 361 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 362 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 363 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ierr", "terr", "abort", "resp",
+					  "cmd", "ibi", "rx", "tx", "rcv",
+					  "st", "sp", "tend", "nack", "al",
+					  "tmo", "wu";
+			clocks = <&cpg CPG_MOD R9A08G046_I3C_PCLK>,
+				 <&cpg CPG_MOD R9A08G046_I3C_TCLK>;
+			clock-names = "pclk", "tclk";
+			resets = <&cpg R9A08G046_I3C_PRESETN>,
+				 <&cpg R9A08G046_I3C_TRESETN>;
+			reset-names = "presetn", "tresetn";
+			power-domains = <&cpg>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		ssi0: ssi at 100e4000 {
 			compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi";
 			reg = <0 0x100e4000 0 0x400>;
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
index 68d7b579e352..0be2936f9424 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
@@ -13,6 +13,7 @@
 #define SW_DPI_EN		0
 #define SW_GPIO4		1
 #define SW_I3C_EN		0
+#define SW_I3C_IOVS		0
 #define SW_SER0_PMOD		1
 
 #define PMOD_GPIO4		0
@@ -174,6 +175,16 @@ pcie_pins: pcie {
 		pinmux = <RZG3L_PORT_PINMUX(G, 7, 1)>; /* PCIE_RST_OUT# */
 	};
 
+	i3c_pins: i3c {
+		pinmux = <RZG3L_PORT_PINMUX(2, 0, 2)>, /* I3C_SCL */
+			 <RZG3L_PORT_PINMUX(2, 1, 2)>; /* I3C_SDA */
+#if SW_I3C_IOVS
+		power-source = <1800>;
+#else
+		power-source = <1200>;
+#endif
+	};
+
 	rsci1_pins: rsci1 {
 		pinmux = <RZG3L_PORT_PINMUX(D, 4, 5)>, /* RSCI1_RXD_MISO_SCL */
 			 <RZG3L_PORT_PINMUX(D, 5, 5)>, /* RSCI1_TXD_MOSI_SDA */
@@ -250,6 +261,16 @@ &rsci3 {
 };
 #endif
 
+#if SW_I3C_EN
+&i3c {
+	pinctrl-0 = <&i3c_pins>;
+	pinctrl-names = "default";
+	i2c-scl-hz = <400000>;
+	i3c-scl-hz = <12500000>;
+	status = "okay";
+};
+#endif
+
 #if !SW_DPI_EN
 &rspi2 {
 	pinctrl-0 = <&rspi2_pins>;
diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
index 91b2d0d43104..5959e62ad7ed 100644
--- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
@@ -13,6 +13,10 @@
  *      0 - SMARC_I2C_GP is enabled
  *      1 - I3C is enabled
  *
+ * Switch position SYS.3, Macro SW_I3C_IOVS:
+ *      0 - I3C voltage is 1.2V (when SW_I3C_EN == 1)
+ *      1 - I3C voltage is 1.8V
+ *
  * Switch position SYS.4, Macro SW_SD2_EN:
  *      0 - Select I2S0
  *      1 - Select SD2

-- 
2.56.0