[PATCH v4 6/6] i3c: mipi-i3c-hci: Add a quirk to set Response buffer threshold

[Jarkko Nikula]

On 8/21/24 4:35 PM, Shyam Sundar S K wrote:
> The current driver sets the response buffer threshold value to 1
> (N+1, 2 DWORDS) in the QUEUE THRESHOLD register. However, the AMD
> I3C controller only generates interrupts when the response buffer
> threshold value is set to 0 (1 DWORD).
> 
> Therefore, a quirk is added to set the response buffer threshold value
> to 0.
> 
> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m at amd.com>
> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m at amd.com>
> Co-developed-by: Guruvendra Punugupati <Guruvendra.Punugupati at amd.com>
> Signed-off-by: Guruvendra Punugupati <Guruvendra.Punugupati at amd.com>
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k at amd.com>
> ---
>   drivers/i3c/master/mipi-i3c-hci/core.c       |  6 +++++-
>   drivers/i3c/master/mipi-i3c-hci/hci.h        |  2 ++
>   drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 11 +++++++++++
>   3 files changed, 18 insertions(+), 1 deletion(-)
> 
Reviewed-by: Jarkko Nikula <jarkko.nikula at linux.intel.com>