[PATCH v1 7/8] iommu: Park TDISP T=0 devices in the blocking domain

Jason Gunthorpe jgg at nvidia.com
Wed Oct 28 08:09:09 PDT 2026


On Wed, Oct 28, 2026 at 02:19:17PM +0000, Shameer Kolothum Thodi wrote:
> > +	/*
> > +	 * When in T=0 mode the T=1 vIOMMU must always be set to
> > BLOCKED to
> > +	 * release control of ATS.
> > +	 */
> > +	if (iommu_using_t0_stream(first)) {
> > +		if (!ops->blocked_domain)
> > +			return ERR_PTR(-EINVAL);
> > +		return ops->blocked_domain;
> 
> How is MSI allocation handled for T=0 devices? The ITS calls
> iommu_dma_prepare_msi(), which appears to return -EOPNOTSUPP
> for the blocked domain. Is that intentional?

For a TDISP capable devince MSI is always issued using T=0, meaning it
does not go through the SMMU. It should be wired to defeat
iommu_dma_prepare_msi() and use an identity IOVA as though there is no
iommu present..

AFAIK this is true for all devices all arches today.

Jason



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