[PATCH v3 2/6] dt-bindings: phy: Add rockchip,rk3568-edp-phy

[Damon Ding]

Hi Rob,

On 10/21/2026 9:34 PM, Rob Herring wrote:
> On Tue, Oct 20, 2026 at 11:09:12AM +0800, Damon Ding wrote:
>> Document the eDP transmitter PHY with NaNeng IP block found on the
>> RK3568 SoC.  The PHY is controlled through the eDP PHY GRF registers,
>> so its node is modeled as a child of the eDP PHY GRF syscon.  Also
>> add the "rockchip,rk3568-edp-phy-grf" compatible and the "edp-phy"
>> child node reference to the Rockchip GRF schema.
>>
>> Signed-off-by: Damon Ding <damon.ding at rock-chips.com>
>> ---
>>   .../bindings/phy/rockchip,rk3568-edp-phy.yaml | 59 +++++++++++++++++++
>>   .../devicetree/bindings/soc/rockchip/grf.yaml | 15 +++++
>>   2 files changed, 74 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml
>> new file mode 100644
>> index 000000000000..afe7bc3d839e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3568-edp-phy.yaml
>> @@ -0,0 +1,59 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/rockchip,rk3568-edp-phy.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Rockchip eDP Transmitter PHY with NaNeng IP block
>> +
>> +maintainers:
>> +  - Damon Ding <damon.ding at rock-chips.com>
>> +  - Heiko Stuebner <heiko at sntech.de>
>> +
>> +description:
>> +  On the RK3568 SoC the eDP PHY is controlled through the eDP PHY GRF
>> +  registers, therefore the PHY node is expected to be a child of the
>> +  eDP PHY GRF syscon node.
> 
>  From the driver, looks like there is a specific register range for the
> phy regs in the GRF, so please add a 'reg' entry (and 'ranges' in the
> parent).
> 

I see. For v4, I will add the reg entry for the PHY node and ranges in 
the parent syscon node, as done in rk3399-emmc-phy.

The proposed eDP PHY DT layout looks like:

edp_phy_grf: syscon at fdcb0000 {
   compatible = "rockchip,rk3568-edp-phy-grf", "syscon", "simple-mfd";
   reg = <0x0 0xfdcb0000 0x0 0x100>;
   clocks = <&cru PCLK_EDPPHY_GRF>;
   #address-cells = <1>;
   #size-cells = <1>;
   ranges;

   edp_phy: phy at 0 {
	compatible = "rockchip,rk3568-edp-phy";
	reg = <0x0 0x100>;
	clocks = <&pmucru XIN_OSC0_EDPPHY_G>;
	clock-names = "refclk";
	#phy-cells = <0>;
   };
};

The driver will be updated accordingly to map its own registers
via devm_platform_ioremap_resource() + devm_regmap_init_mmio() instead 
of accessing them through the parent syscon regmap.

Best regards,
Damon