[PATCH 3/6] dt-bindings: mailbox: Add AMD PL Mailbox IP

[Ben Levinsky]

> 
> 
> *From: *Krzysztof Kozlowski <krzk at kernel.org>
> *Date: *Thursday, October 15, 2026 at 2:46 AM
> *To: *Levinsky, Ben <ben.levinsky at amd.com>
> *Cc: *jassisinghbrar at gmail.com <jassisinghbrar at gmail.com>; andersson at kernel.org 
> <andersson at kernel.org>; mathieu.poirier at linaro.org <mathieu.poirier at linaro.org>; 
> robh at kernel.org <robh at kernel.org>; krzk+dt at kernel.org <krzk+dt at kernel.org>; 
> conor+dt at kernel.org <conor+dt at kernel.org>; Simek, Michal <michal.simek at amd.com>; 
> linux-remoteproc at vger.kernel.org <linux-remoteproc at vger.kernel.org>; 
> devicetree at vger.kernel.org <devicetree at vger.kernel.org>; linux-arm- 
> kernel at lists.infradead.org <linux-arm-kernel at lists.infradead.org>; linux- 
> kernel at vger.kernel.org <linux-kernel at vger.kernel.org>; Shah, Tanmay 
> <tanmay.shah at amd.com>
> *Subject: *Re: [PATCH 3/6] dt-bindings: mailbox: Add AMD PL Mailbox IP
> 
> On Wed, Oct 14, 2026 at 02:34:23PM -0700, Ben Levinsky wrote:
>  > Document the AMD programmable-logic Mailbox IP used for bidirectional
>  > FIFO communication between two processor-facing interfaces.
>  >
>  > The same IP is used on ZynqMP, Versal, Versal NET and Versal Gen 2.
>  > Name each SoC in its compatible, and use amd,zynqmp-pl-mbox-2.1 as the
>  > fallback that drivers match.
>  >
>  > Define the transmit and receive channel indices together with the register
>  > aperture, interrupt, and interface clock. Describe the FIFO depth chosen
>  > when the IP is configured, so that the driver can size received messages
>  > to it.
>  >
>  > Assisted-by: LLM sparse
> 
> How sparse assists here? It's something new. Since when does it parse
> yaml code?

  Hi Krzysztof,

  Thank you for the review.

  You are right, sparse was not used for this patch. It was only run on
  the C patches of the series, and I applied the same trailer to the
  whole series by mistake. In v2 the binding patches will name only the
  model, and the tool list will match what was actually used on each
  patch.

> 
>  > Signed-off-by: Ben Levinsky <ben.levinsky at amd.com>
>  > ---
>  >  .../mailbox/amd,zynqmp-pl-mbox-2.1.yaml       | 74 +++++++++++++++++++
>  >  1 file changed, 74 insertions(+)
>  >  create mode 100644 Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl- 
> mbox-2.1.yaml
>  >
>  > diff --git a/Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl- 
> mbox-2.1.yaml b/Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl- 
> mbox-2.1.yaml
>  > new file mode 100644
>  > index 000000000000..2cc0d106b888
>  > --- /dev/null
>  > +++ b/Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl-mbox-2.1.yaml
>  > @@ -0,0 +1,74 @@
>  > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>  > +%YAML 1.2
>  > +---
>  > +$id: http://devicetree.org/schemas/mailbox/amd,zynqmp-pl-mbox-2.1.yaml# 
> <http://devicetree.org/schemas/mailbox/amd,zynqmp-pl-mbox-2.1.yaml#>
>  > +$schema: http://devicetree.org/meta-schemas/core.yaml# <http:// 
> devicetree.org/meta-schemas/core.yaml#>
>  > +
>  > +title: AMD Programmable Logic Mailbox IP
>  > +
>  > +maintainers:
>  > +  - Ben Levinsky <ben.levinsky at amd.com>
>  > +
>  > +description: |
>  > +  The AMD Programmable Logic Mailbox IP provides bidirectional message passing
>  > +  between two processor-facing interfaces. Each interface writes messages to
>  > +  a send FIFO and reads messages from a receive FIFO. The register aperture,
>  > +  interrupt, and clock described by a node belong to one processor-facing
>  > +  interface. Channel 0 represents transmit and channel 1 represents receive
>  > +  for that interface.
>  > +
>  > +properties:
>  > +  compatible:
>  > +    oneOf:
>  > +      - const: amd,zynqmp-pl-mbox-2.1
> 
> What is 2.1? Your SoC has different versions?

  2.1 is the version of the Mailbox IP core in the Xilinx IP catalog
  (Mailbox v2.1). It is not a SoC version. The IP is synthesized into the
  programmable logic, so the same core is used on every SoC, and the SoC
  names in the compatibles do not add information.

  In v2 I will use a single IP-versioned compatible, "xlnx,mailbox-2.1",
  and drop the SoC-specific ones. This is also the compatible the Xilinx
  device tree generator already emits for this IP.

> 
>  > +      - items:
>  > +          - enum:
>  > +              - amd,versal-pl-mbox-2.1
>  > +              - amd,versal-net-pl-mbox-2.1
>  > +              - amd,versal2-pl-mbox-2.1
>  > +          - const: amd,zynqmp-pl-mbox-2.1
>  > +
>  > +  reg:
>  > +    maxItems: 1
>  > +
>  > +  interrupts:
>  > +    maxItems: 1
>  > +
>  > +  clocks:
>  > +    maxItems: 1
>  > +
>  > +  amd,mbox-pl-fifo-len:
>  > +    $ref: /schemas/types.yaml#/definitions/uint32
>  > +    minimum: 16
>  > +    maximum: 8192
>  > +    default: 16
>  > +    description:
>  > +      Depth of the send and receive FIFOs in 32-bit words, as configured by
>  > +      the C_MAILBOX_DEPTH parameter of the IP. Must match the configured
>  > +      depth.
> 
> So you have multiple mailboxes per one soc different in this?

  Yes. The FIFO depth is chosen per IP instance when the design is
  synthesized, so one design can contain several mailboxes with different
  depths. The depth cannot be read from the registers, so the driver
  needs it from the device tree to size its receive buffer and to limit
  transmit messages. In v2 I will rename the property to
  "xlnx,mailbox-depth", after the IP parameter, and state this in its
  description.

  Thanks,
  Ben

> 
> Best regards,
> Krzysztof
>