[PATCH v7 0/2] Add initial support for Qualcomm Kuno SoC
Hardeep Sharma
hardeep.sharma at oss.qualcomm.com
Wed Oct 7 20:11:57 PDT 2026
On 9/29/2026 3:18 PM, Hardeep Sharma wrote:
> This series adds initial support for the Qualcomm Kuno SoC and the Kuno
> IDP reference board.
>
> Kuno is a 32-bit ARM (Cortex-A7) Qualcomm platform. The rest of the
> series (bindings, GCC, RPMh clocks and power domains, interconnect,
> pinctrl, geni-se) has been applied and is in linux-next, so v7 carries
> only the SoC and IDP board devicetree, plus a small geni-se binding
> update that lets the QUP wrapper use one address/size cell on 32-bit
> SoCs.
>
> Signed-off-by: Hardeep Sharma <hardeep.sharma at oss.qualcomm.com>
> ---
> Changes in v7:
> - Addressed v6 review feedback:
> - New patch: allow 1 or 2 #address-cells/#size-cells in the geni-se
> QUP wrapper binding.
> - Switched the QUP wrapper to one address/size cell with an empty
> ranges, instead of the explicit 32-bit window.
> - Link to v6: https://lore.kernel.org/all/20260929-kuno-soc-support-v6-1-a16afafbcbc7@oss.qualcomm.com/
>
> Changes in v6:
> - Rebased on next-20260928. The rest of the series has been applied,
> so only the devicetree patch remains.
> - Addressed v5 review feedback:
> - Added the full qcom,pdc-ranges map (22 ranges instead of 3), so
> that all PDC-routed wakeup GPIOs can wake the system.
> - Added wakeup-parent = <&pdc> to the TLMM node.
> - Replaced the explicit soc ranges with an empty ranges and named the
> node soc, matching the other 32-bit Qualcomm SoCs.
> - Widened the QUP wrapper ranges to cover the whole 32-bit address
> space instead of a 16 MiB window.
> - Link to v5: https://lore.kernel.org/all/20260827-kuno-soc-support-v5-0-6d47636a8f09@oss.qualcomm.com/
>
> Changes in v5:
> - Selected QCOM_GDSC from the Kuno GCC config. The driver registers GDSCs
> (added in v4), so like the other Qualcomm GCC drivers it must select
> QCOM_GDSC; otherwise, in a configuration where nothing else enables it
> (e.g. COMPILE_TEST or a minimal Kuno-only build), gdsc_register() returns
> -ENOSYS and the clock controller fails to probe.
> - Link to v4: https://lore.kernel.org/all/20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com/
>
> Changes in v4:
> - Addressed v3 review feedback:
> - Registered the interconnect NoC provider from an explicit
> core_initcall() instead of module_platform_driver(), matching the
> established qcom interconnect driver convention.
> - Replaced the NA mux-slot placeholder with _ across the pinctrl
> PINGROUP table, matching the upstream qcom pinctrl convention.
> - Added minItems: 1 to the interconnect binding clocks property so a
> single clock is valid (system-noc), and aligned the binding
> examples with the sdx75 labelled-node style.
> - Added GDSC power-domain support to the Kuno GCC: the binding now
> defines GDSC macros and the driver registers the EMAC0, PCIe and
> USB20 GDSCs, so #power-domain-cells has real backing providers.
> - Split the cpu-idle-states phandle list so each phandle is on its
> own line.
> - Collected Acked-by / Reviewed-by tags from v3.
> - Link to v3: https://lore.kernel.org/all/20260821-kuno-soc-support-v3-0-196e2b306368@oss.qualcomm.com/
>
> Changes in v3:
> - Addressed v2 review feedback:
> - Reworked the interconnect binding clocks: dropped clock-names and
> replaced the flexible min/maxItems list with fixed per-compatible
> clocks (aggre-noc: 2, system-noc: 1), required where present and
> disallowed otherwise, matching the sdx75/glymur shape.
> - Made #power-domain-cells required on the Kuno GCC binding and
> declared it on the SoC gcc node, since the Kuno GCC hosts GDSCs and
> is a power-domain provider (following qcom,sdx75-gcc); the driver's
> GDSC support will follow separately.
> - Made the GPIO65/66 QDSS CTI trig1 funcsel-3 route selectable: added
> a distinct qdss_cti_trig1_mire pin function (and allowed it in the
> TLMM binding enum), as the duplicate funcsel-2/3 entry left
> funcsel-3 unreachable.
> - Collected Acked-by / Reviewed-by tags from v2.
> - Link to v2: https://lore.kernel.org/all/20260814-kuno-soc-support-v2-0-3079794f0f73@oss.qualcomm.com/
>
> Changes in v2:
> - Addressed v1 review feedback:
> - Reworked soc: qcom: geni-se commit message; dropped the Fixes: tag.
> - Reworded dt-bindings commit messages to the "Document X for the
> Qualcomm Kuno SoC" one-liner form.
> - Canonicalized copyright headers on interconnect binding / driver /
> NoC ID header to the single-line Qualcomm Technologies form.
> - Dropped unused <linux/mod_devicetable.h> from the interconnect
> driver.
> - Fixed MODULE_DESCRIPTION casing "KUNO" -> "Kuno" in the interconnect
> driver.
> - Extended interconnect binding to optionally allow up to four QoS AHB
> clocks (matches sdx75/glymur shape).
> - Cleaned up brace/space style in gcc-kuno.c to match peer clock
> drivers.
> - Reworked initial DTS: moved idle-states / domain-idle-states inside
> cpus{}, wrapped fixed clocks in a clocks{} container with peer node
> names (xo-board, sleep-clk), dropped the pcie_pipe_clk fixed-clock
> stub (the GCC 4th clock now uses <0> in DTS to match the sdx75
> idiom; the YAML example uses a named placeholder), dropped the
> RPMHPD_CX power-domain reference on GCC (Kuno GCC has no GDSCs /
> no corner votes / no pm_runtime, so the reference was inert), and
> added a bootloader hand-off comment on the memory node.
> - Collected Acked-by / Reviewed-by tags from v1.
> - Link to v1: https://lore.kernel.org/all/20260809-kuno-soc-support-v1-0-5e0ede4a0c72@oss.qualcomm.com/
>
> ---
> Hardeep Sharma (2):
> dt-bindings: soc: qcom,geni-se: Allow 1 or 2 address and size cells
> ARM: dts: qcom: Add initial device tree for Kuno SoC
>
> .../devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 4 +-
> arch/arm/boot/dts/qcom/Makefile | 1 +
> arch/arm/boot/dts/qcom/qcom-kuno-idp.dts | 25 ++
> arch/arm/boot/dts/qcom/qcom-kuno.dtsi | 444 +++++++++++++++++++++
> 4 files changed, 472 insertions(+), 2 deletions(-)
> ---
> base-commit: 6375e61c01e93e35ee7acd336a689ac1fae4b509
> change-id: 20260809-kuno-soc-support-1dab826de0bf
>
> Best regards,
> --
> Hardeep Sharma <hardeep.sharma at oss.qualcomm.com>
Hello All,
Both of the following patches are ready to be picked:
[PATCH v7 1/2] dt-bindings: soc: qcom,geni-se: Allow 1 or 2 address and
size cells
[PATCH v7 2/2] ARM: dts: qcom: Add initial device tree for Kuno SoC
Could you please pick them ?
Thank you for your review and support.
Best Wishes
Hardeep Sharma
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