[PATCH 1/5] clocksource: timer-cadence-ttc: Move register definitions to shared header

[Meher Thanmaiee]

Move the Cadence TTC register offsets and existing bit-field definitions
from timer-cadence-ttc.c into a new include/linux/timer-cadence-ttc.h
header. While moving them, convert bit-mask definitions to use BIT()
and GENMASK() macros.

The shared header will be reused by subsequent patches adding PWM
support for Cadence TTC.

Signed-off-by: Meher Thanmaiee <meherthanmaiee.vanukuri at amd.com>
---
 MAINTAINERS                             |  1 +
 drivers/clocksource/timer-cadence-ttc.c | 18 +-----------------
 include/linux/timer-cadence-ttc.h       | 28 ++++++++++++++++++++++++++++
 3 files changed, 30 insertions(+), 17 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 65e8a4b5c90b..b25ad0c18ffd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3922,6 +3922,7 @@ F:	drivers/edac/synopsys_edac.c
 F:	drivers/i2c/busses/i2c-cadence.c
 F:	drivers/i2c/busses/i2c-xiic.c
 F:	drivers/mmc/host/sdhci-of-arasan.c
+F:	include/linux/timer-cadence-ttc.h
 N:	zynq
 N:	xilinx
 
diff --git a/drivers/clocksource/timer-cadence-ttc.c b/drivers/clocksource/timer-cadence-ttc.c
index 3c50d6892849..8be13d344007 100644
--- a/drivers/clocksource/timer-cadence-ttc.c
+++ b/drivers/clocksource/timer-cadence-ttc.c
@@ -18,6 +18,7 @@
 #include <linux/sched_clock.h>
 #include <linux/module.h>
 #include <linux/of_platform.h>
+#include <linux/timer-cadence-ttc.h>
 
 /*
  * This driver configures the 2 16/32-bit count-up timers as follows:
@@ -34,23 +35,6 @@
  * obtained from device tree. The pre-scaler of 32 is used.
  */
 
-/*
- * Timer Register Offset Definitions of Timer 1, Increment base address by 4
- * and use same offsets for Timer 2
- */
-#define TTC_CLK_CNTRL_OFFSET		0x00 /* Clock Control Reg, RW */
-#define TTC_CNT_CNTRL_OFFSET		0x0C /* Counter Control Reg, RW */
-#define TTC_COUNT_VAL_OFFSET		0x18 /* Counter Value Reg, RO */
-#define TTC_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
-#define TTC_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
-#define TTC_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */
-
-#define TTC_CNT_CNTRL_DISABLE_MASK	0x1
-
-#define TTC_CLK_CNTRL_CSRC_MASK		(1 << 5)	/* clock source */
-#define TTC_CLK_CNTRL_PSV_MASK		0x1e
-#define TTC_CLK_CNTRL_PSV_SHIFT		1
-
 /*
  * Setup the timers to use pre-scaling, using a fixed value for now that will
  * work across most input frequency, but it may need to be more dynamic
diff --git a/include/linux/timer-cadence-ttc.h b/include/linux/timer-cadence-ttc.h
new file mode 100644
index 000000000000..4f2b85e0ff78
--- /dev/null
+++ b/include/linux/timer-cadence-ttc.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Shared definitions for the Cadence Triple Timer Counter (TTC).
+ *
+ * Copyright (C) 2011 - 2013, Xilinx, Inc.
+ * Copyright (C) 2026, Advanced Micro Devices, Inc.
+ */
+
+#ifndef _LINUX_TIMER_CADENCE_TTC_H
+#define _LINUX_TIMER_CADENCE_TTC_H
+
+#include <linux/bits.h>
+
+/* Timer Register Offset Definitions of Timer 1 */
+#define TTC_CLK_CNTRL_OFFSET		0x00 /* Clock Control Reg, RW */
+#define TTC_CNT_CNTRL_OFFSET		0x0C /* Counter Control Reg, RW */
+#define TTC_COUNT_VAL_OFFSET		0x18 /* Counter Value Reg, RO */
+#define TTC_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
+#define TTC_ISR_OFFSET			0x54 /* Interrupt Status Reg, RO */
+#define TTC_IER_OFFSET			0x60 /* Interrupt Enable Reg, RW */
+
+#define TTC_CNT_CNTRL_DISABLE_MASK	BIT(0)
+
+#define TTC_CLK_CNTRL_CSRC_MASK		BIT(5) /* clock source */
+#define TTC_CLK_CNTRL_PSV_MASK		GENMASK(4, 1)
+#define TTC_CLK_CNTRL_PSV_SHIFT		1
+
+#endif /* _LINUX_TIMER_CADENCE_TTC_H */

-- 
2.34.1