[PATCH net-next v4 5/6] net: phy: mediatek: add calibration logic for AN7581

[Andrew Lunn]

> It's safe in the measure that the worst is that link goes down during the
> calibration... I will rework the function to assign the base address to the
> default address for port 0 (it's hardcoded by the SoC) and use the lock and
> read/write helper instead.

Are there multiple PHYs in the package? What happens if both are doing
calibration at the same time?

PHY #0                            PHY #1


phy_modify_mmd(phydev, devad, regnum, mask, cal_val);

		       	      	  phy_modify_mmd(phydev, devad, regnum, mask, cal_val);
				  ret = mtk_cal_cycle_wait(phydev_p0);

ret = mtk_cal_cycle_wait(phydev_p0);

    Andrew