[PATCH RFC v3 13/17] riscv: dts: zhihe: add A210 UARTs
Han Gao via B4 Relay
devnull+gaohan.iscas.ac.cn at kernel.org
Mon Nov 2 11:45:16 PST 2026
From: Zhiguo Zhu <zhiguo.zhu at linux.alibaba.com>
Describe the ten DW APB UARTs with SCMI clocks and their separate APB
and serial resets.
Signed-off-by: Zhiguo Zhu <zhiguo.zhu at linux.alibaba.com>
Signed-off-by: Han Gao <gaohan at iscas.ac.cn>
---
arch/riscv/boot/dts/zhihe/a210.dtsi | 160 ++++++++++++++++++++++++++++++++++++
1 file changed, 160 insertions(+)
diff --git a/arch/riscv/boot/dts/zhihe/a210.dtsi b/arch/riscv/boot/dts/zhihe/a210.dtsi
index 6d85d94f0af1..caa3005830ca 100644
--- a/arch/riscv/boot/dts/zhihe/a210.dtsi
+++ b/arch/riscv/boot/dts/zhihe/a210.dtsi
@@ -353,6 +353,70 @@ mbox_e902: mailbox at 320000 {
#mbox-cells = <1>;
};
+ uart0: serial at 2014000 {
+ compatible = "zhihe,a210-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x02014000 0x0 0x1000>;
+ clocks = <&scmi_clk A210_CLK_UART_SCLK(0)>,
+ <&scmi_clk A210_CLK_UART_PCLK(0)>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupt-parent = <&intc>;
+ interrupts = <321 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ resets = <&scmi_reset A210_RESET_UART_PRST(0)>,
+ <&scmi_reset A210_RESET_UART_SRST(0)>;
+
+ status = "disabled";
+ };
+
+ uart1: serial at 2015000 {
+ compatible = "zhihe,a210-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x02015000 0x0 0x1000>;
+ clocks = <&scmi_clk A210_CLK_UART_SCLK(1)>,
+ <&scmi_clk A210_CLK_UART_PCLK(1)>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupt-parent = <&intc>;
+ interrupts = <322 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ resets = <&scmi_reset A210_RESET_UART_PRST(1)>,
+ <&scmi_reset A210_RESET_UART_SRST(1)>;
+
+ status = "disabled";
+ };
+
+ uart2: serial at 2016000 {
+ compatible = "zhihe,a210-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x02016000 0x0 0x1000>;
+ clocks = <&scmi_clk A210_CLK_UART_SCLK(2)>,
+ <&scmi_clk A210_CLK_UART_PCLK(2)>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupt-parent = <&intc>;
+ interrupts = <323 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ resets = <&scmi_reset A210_RESET_UART_PRST(2)>,
+ <&scmi_reset A210_RESET_UART_SRST(2)>;
+
+ status = "disabled";
+ };
+
+ uart3: serial at 2017000 {
+ compatible = "zhihe,a210-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x02017000 0x0 0x1000>;
+ clocks = <&scmi_clk A210_CLK_UART_SCLK(3)>,
+ <&scmi_clk A210_CLK_UART_PCLK(3)>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupt-parent = <&intc>;
+ interrupts = <324 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ resets = <&scmi_reset A210_RESET_UART_PRST(3)>,
+ <&scmi_reset A210_RESET_UART_SRST(3)>;
+
+ status = "disabled";
+ };
+
peri1_padctrl: pinctrl at 2026000 {
compatible = "zhihe,a210-peri1-pinctrl";
reg = <0x0 0x02026000 0x0 0x1000>;
@@ -363,6 +427,102 @@ peri1_padctrl: pinctrl at 2026000 {
status = "disabled";
};
+ uart4: serial at 8401000 {
+ compatible = "zhihe,a210-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x08401000 0x0 0x1000>;
+ clocks = <&scmi_clk A210_CLK_UART_SCLK(4)>,
+ <&scmi_clk A210_CLK_UART_PCLK(4)>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupt-parent = <&intc>;
+ interrupts = <325 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ resets = <&scmi_reset A210_RESET_UART_PRST(4)>,
+ <&scmi_reset A210_RESET_UART_SRST(4)>;
+
+ status = "disabled";
+ };
+
+ uart5: serial at 8402000 {
+ compatible = "zhihe,a210-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x08402000 0x0 0x1000>;
+ clocks = <&scmi_clk A210_CLK_UART_SCLK(5)>,
+ <&scmi_clk A210_CLK_UART_PCLK(5)>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupt-parent = <&intc>;
+ interrupts = <326 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ resets = <&scmi_reset A210_RESET_UART_PRST(5)>,
+ <&scmi_reset A210_RESET_UART_SRST(5)>;
+
+ status = "disabled";
+ };
+
+ uart6: serial at 8403000 {
+ compatible = "zhihe,a210-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x08403000 0x0 0x1000>;
+ clocks = <&scmi_clk A210_CLK_UART_SCLK(6)>,
+ <&scmi_clk A210_CLK_UART_PCLK(6)>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupt-parent = <&intc>;
+ interrupts = <327 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ resets = <&scmi_reset A210_RESET_UART_PRST(6)>,
+ <&scmi_reset A210_RESET_UART_SRST(6)>;
+
+ status = "disabled";
+ };
+
+ uart7: serial at 8404000 {
+ compatible = "zhihe,a210-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x08404000 0x0 0x1000>;
+ clocks = <&scmi_clk A210_CLK_UART_SCLK(7)>,
+ <&scmi_clk A210_CLK_UART_PCLK(7)>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupt-parent = <&intc>;
+ interrupts = <328 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ resets = <&scmi_reset A210_RESET_UART_PRST(7)>,
+ <&scmi_reset A210_RESET_UART_SRST(7)>;
+
+ status = "disabled";
+ };
+
+ uart8: serial at 8405000 {
+ compatible = "zhihe,a210-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x08405000 0x0 0x1000>;
+ clocks = <&scmi_clk A210_CLK_UART_SCLK(8)>,
+ <&scmi_clk A210_CLK_UART_PCLK(8)>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupt-parent = <&intc>;
+ interrupts = <329 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ resets = <&scmi_reset A210_RESET_UART_PRST(8)>,
+ <&scmi_reset A210_RESET_UART_SRST(8)>;
+
+ status = "disabled";
+ };
+
+ uart9: serial at 8406000 {
+ compatible = "zhihe,a210-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x08406000 0x0 0x1000>;
+ clocks = <&scmi_clk A210_CLK_UART_SCLK(9)>,
+ <&scmi_clk A210_CLK_UART_PCLK(9)>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupt-parent = <&intc>;
+ interrupts = <330 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ resets = <&scmi_reset A210_RESET_UART_PRST(9)>,
+ <&scmi_reset A210_RESET_UART_SRST(9)>;
+
+ status = "disabled";
+ };
+
peri2_padctrl: pinctrl at 8411000 {
compatible = "zhihe,a210-peri2-pinctrl";
reg = <0x0 0x08411000 0x0 0x1000>;
--
2.55.0
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