[PATCH RFC v3 12/17] riscv: dts: zhihe: add A210 core support
Han Gao via B4 Relay
devnull+gaohan.iscas.ac.cn at kernel.org
Mon Nov 2 11:45:15 PST 2026
From: Zhiguo Zhu <zhiguo.zhu at linux.alibaba.com>
Describe the CPU clusters, interrupt controllers and pad controllers.
Use SCMI clock and reset services through the E902 mailbox, with a
second mailbox channel for firmware notifications.
The SCMI clock and reset IDs are assigned by the E902 firmware, so they
live in headers next to the DTS rather than in dt-bindings.
Signed-off-by: Zhiguo Zhu <zhiguo.zhu at linux.alibaba.com>
Signed-off-by: Han Gao <gaohan at iscas.ac.cn>
---
arch/riscv/boot/dts/zhihe/a210-clock.h | 15 ++
arch/riscv/boot/dts/zhihe/a210-reset.h | 13 +
arch/riscv/boot/dts/zhihe/a210.dtsi | 433 +++++++++++++++++++++++++++++++++
3 files changed, 461 insertions(+)
diff --git a/arch/riscv/boot/dts/zhihe/a210-clock.h b/arch/riscv/boot/dts/zhihe/a210-clock.h
new file mode 100644
index 000000000000..d57e99dfd3e3
--- /dev/null
+++ b/arch/riscv/boot/dts/zhihe/a210-clock.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+#ifndef __A210_CLOCK_H
+#define __A210_CLOCK_H
+
+/* SCMI clock IDs as numbered by the E902 firmware */
+#define A210_CLK_UART_SCLK(n) (n)
+#define A210_CLK_UART_PCLK(n) (10 + (n))
+#define A210_CLK_PERI1_PAD 20
+#define A210_CLK_PERI2_PAD 21
+#define A210_CLK_PERI3_PAD 22
+#define A210_CLK_AON_SYS 23
+#define A210_CLK_AON_I2C1_IC 24
+#define A210_CLK_AON_I2C1_PCLK 25
+
+#endif
diff --git a/arch/riscv/boot/dts/zhihe/a210-reset.h b/arch/riscv/boot/dts/zhihe/a210-reset.h
new file mode 100644
index 000000000000..3f8eaf0fc17b
--- /dev/null
+++ b/arch/riscv/boot/dts/zhihe/a210-reset.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+#ifndef __A210_RESET_H
+#define __A210_RESET_H
+
+/* SCMI reset IDs as numbered by the E902 firmware */
+#define A210_RESET_UART_SRST(n) (n)
+#define A210_RESET_UART_PRST(n) (10 + (n))
+#define A210_RESET_PERI1_PAD 20
+#define A210_RESET_PERI2_PAD 21
+#define A210_RESET_PERI3_PAD 22
+#define A210_RESET_AON_I2C1 23
+
+#endif
diff --git a/arch/riscv/boot/dts/zhihe/a210.dtsi b/arch/riscv/boot/dts/zhihe/a210.dtsi
new file mode 100644
index 000000000000..6d85d94f0af1
--- /dev/null
+++ b/arch/riscv/boot/dts/zhihe/a210.dtsi
@@ -0,0 +1,433 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "a210-clock.h"
+#include "a210-reset.h"
+
+/ {
+ compatible = "zhihe,a210";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <24000000>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&c908_0>;
+ };
+
+ core1 {
+ cpu = <&c908_1>;
+ };
+
+ core2 {
+ cpu = <&c908_2>;
+ };
+
+ core3 {
+ cpu = <&c908_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&c920_4>;
+ };
+
+ core1 {
+ cpu = <&c920_5>;
+ };
+
+ core2 {
+ cpu = <&c920_6>;
+ };
+
+ core3 {
+ cpu = <&c920_7>;
+ };
+ };
+ };
+
+ c0_l2_cache: l2-cache0 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <524288>;
+ cache-unified;
+ };
+
+ c1_l2_cache: l2-cache1 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <1048576>;
+ cache-unified;
+ };
+
+ c908_0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "thead,c908", "riscv";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c0_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c908_1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "thead,c908", "riscv";
+ reg = <1>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c0_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c908_2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "thead,c908", "riscv";
+ reg = <2>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c0_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c908_3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "thead,c908", "riscv";
+ reg = <3>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c0_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c920_4: cpu at 4 {
+ device_type = "cpu";
+ compatible = "thead,c920", "riscv";
+ reg = <4>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <65536>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c1_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu4_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c920_5: cpu at 5 {
+ device_type = "cpu";
+ compatible = "thead,c920", "riscv";
+ reg = <5>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <65536>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c1_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu5_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c920_6: cpu at 6 {
+ device_type = "cpu";
+ compatible = "thead,c920", "riscv";
+ reg = <6>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <65536>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c1_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu6_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c920_7: cpu at 7 {
+ device_type = "cpu";
+ compatible = "thead,c920", "riscv";
+ reg = <7>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <65536>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c1_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu7_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+ };
+
+ firmware {
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&mbox_e902 0>, <&mbox_e902 1>;
+ mbox-names = "tx", "rx";
+ shmem = <&scmi_shmem>, <&scmi_notification_shmem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol at 14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_reset: protocol at 16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ dma-noncoherent;
+ #size-cells = <2>;
+
+ mbox_e902: mailbox at 320000 {
+ compatible = "zhihe,a210-ap-mailbox";
+ reg = <0 0x00320000 0 0x2000>,
+ <0 0x00311000 0 0x1000>;
+ reg-names = "local", "remote";
+ interrupt-parent = <&intc>;
+ interrupts = <336 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
+ peri1_padctrl: pinctrl at 2026000 {
+ compatible = "zhihe,a210-peri1-pinctrl";
+ reg = <0x0 0x02026000 0x0 0x1000>;
+ clocks = <&scmi_clk A210_CLK_PERI1_PAD>;
+ clock-names = "pclk";
+ resets = <&scmi_reset A210_RESET_PERI1_PAD>;
+
+ status = "disabled";
+ };
+
+ peri2_padctrl: pinctrl at 8411000 {
+ compatible = "zhihe,a210-peri2-pinctrl";
+ reg = <0x0 0x08411000 0x0 0x1000>;
+ clocks = <&scmi_clk A210_CLK_PERI2_PAD>;
+ clock-names = "pclk";
+ resets = <&scmi_reset A210_RESET_PERI2_PAD>;
+
+ status = "disabled";
+ };
+
+ intc: interrupt-controller at 18000000 {
+ compatible = "zhihe,a210-plic", "thead,c900-plic";
+ reg = <0x0 0x18000000 0x0 0x04000000>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>,
+ <&cpu4_intc 11>, <&cpu4_intc 9>,
+ <&cpu5_intc 11>, <&cpu5_intc 9>,
+ <&cpu6_intc 11>, <&cpu6_intc 9>,
+ <&cpu7_intc 11>, <&cpu7_intc 9>;
+ riscv,ndev = <351>;
+ };
+
+ clint0: clint at 1c000000 {
+ compatible = "zhihe,a210-clint", "thead,c900-clint";
+ reg = <0x0 0x1c000000 0x0 0x0000d800>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>,
+ <&cpu4_intc 3>, <&cpu4_intc 7>,
+ <&cpu5_intc 3>, <&cpu5_intc 7>,
+ <&cpu6_intc 3>, <&cpu6_intc 7>,
+ <&cpu7_intc 3>, <&cpu7_intc 7>;
+ };
+
+ aon_padctrl: pinctrl at 30848000 {
+ compatible = "zhihe,a210-aon-pinctrl";
+ reg = <0x0 0x30848000 0x0 0x2000>;
+ clocks = <&scmi_clk A210_CLK_AON_SYS>;
+ clock-names = "pclk";
+
+ status = "disabled";
+ };
+
+ sram at 30907c00 {
+ compatible = "mmio-sram";
+ reg = <0 0x30907c00 0 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x30907c00 0x200>;
+
+ scmi_shmem: scp-sram at 0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0 0x100>;
+ };
+
+ scmi_notification_shmem: scp-sram at 100 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x100 0x100>;
+ };
+ };
+ };
+};
--
2.55.0
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