[PATCH] arm64: dts: allwinner: Cubie A5E: enable SPI flash

[Chen-Yu Tsai]

Hi,

On Tue, May 12, 2026 at 6:18 AM Andre Przywara <andre.przywara at arm.com> wrote:
>
> The Cubie A5E board comes with 16MiB of SPI NOR flash.
>
> Enable the SPI0 DT node and describe the configuration.
>
> Signed-off-by: Andre Przywara <andre.przywara at arm.com>
> ---
>  .../boot/dts/allwinner/sun55i-a527-cubie-a5e.dts  | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
> index bfdf1728cd14b..7ad22fc85d1fd 100644
> --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
> @@ -344,6 +344,21 @@ &r_pio {
>         vcc-pm-supply = <&reg_aldo3>;
>  };
>
> +&spi0  {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&spi0_pc_pins>, <&spi0_cs0_pc_pin>,
> +                   <&spi0_hold_pc_pin>, <&spi0_wp_pc_pin>;

This whole thing needs to be an overlay. The HOLD and WP pins
conflict with eMMC usage, so it seems that Radxa only populates
one or the other.

If you look at the pictures on their official website, you'll see the
SPI NOR chip populated, but not the eMMC chip. On the linux-sunxi wiki
page, you'll see the opposite.

And you probably want to enable QSPI, like Sashiko mentioned.


ChenYu


> +       status = "okay";
> +
> +       flash at 0 {
> +               compatible = "winbond,w25q128", "jedec,spi-nor";
> +               reg = <0>;
> +               spi-max-frequency = <40000000>;
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +       };
> +};
> +
>  &uart0 {
>         pinctrl-names = "default";
>         pinctrl-0 = <&uart0_pb_pins>;
> --
> 2.46.4
>