[PATCH v1 1/2] PCI: imx6: Configure REF_USE_PAD before PHY reset for i.MX95

[Hongxing Zhu]

> -----Original Message-----
> From: Hongxing Zhu <hongxing.zhu at nxp.com>
> Sent: Tuesday, May 12, 2026 1:23 PM
> To: Frank Li <frank.li at nxp.com>; l.stach at pengutronix.de; lpieralisi at kernel.org;
> kwilczynski at kernel.org; mani at kernel.org; robh at kernel.org;
> bhelgaas at google.com; s.hauer at pengutronix.de; kernel at pengutronix.de;
> festevam at gmail.com
> Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> imx at lists.linux.dev; linux-kernel at vger.kernel.org; Hongxing Zhu
> <hongxing.zhu at nxp.com>; stable at vger.kernel.org
> Subject: [PATCH v1 1/2] PCI: imx6: Configure REF_USE_PAD before PHY reset for
> i.MX95
> 
> According to the i.MX95 PCIe PHY Databook, the ref_use_pad signal in the
> Common Block Signals section selects the reference clock source connected to
> the PHY pads. Per the specification, any change to this input must be followed by
> a PHY reset assertion to take effect.
> 
> Move the REF_USE_PAD configuration before the PHY reset toggle to comply with
> the required initialization sequence.
> 
> Fixes: 47f54a902dcd ("PCI: imx6: Toggle the core reset for i.MX95 PCIe")
> Cc: <stable at vger.kernel.org>
> Signed-off-by: Richard Zhu <hongxing.zhu at nxp.com>
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 27 ++++++++++++++++++++++++---
>  1 file changed, 24 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> b/drivers/pci/controller/dwc/pci-imx6.c
> index 1034ac5c5f5c1..c57f18d9e4ffa 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -137,6 +137,7 @@ struct imx_pcie_drvdata {
>  	const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
>  	const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
>  	const struct pci_epc_features *epc_features;
> +	int (*init_pre_reset)(struct imx_pcie *pcie);
>  	int (*init_phy)(struct imx_pcie *pcie);
>  	int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
>  	int (*core_reset)(struct imx_pcie *pcie, bool assert); @@ -247,6 +248,24
> @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
>  	return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 :
> IOMUXC_GPR14;  }
> 
> +static int imx95_pcie_init_pre_reset(struct imx_pcie *imx_pcie) {
> +	bool ext = imx_pcie->enable_ext_refclk;
> +
> +	/*
> +	 * Regarding the Signal Descriptions of i.MX95 PCIe PHY, ref_use_pad is
> +	 * used to select reference clock connected to a pair of pads.
> +	 *
> +	 * Any change in this input must be followed by phy_reset assertion.
> +	 */
> +
> +	regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_SS_RW_REG_0,
Sorry, the register name IMX95_PCIE_SS_RW_REG_0 is incorrect and should be
replaced with IMX95_PCIE_PHY_GEN_CTRL. I will update this in the next version.

> +			   IMX95_PCIE_REF_USE_PAD,
> +			   ext ? IMX95_PCIE_REF_USE_PAD : 0);
> +
> +	return 0;
> +}
> +
>  static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)  {
>  	bool ext = imx_pcie->enable_ext_refclk; @@ -269,9 +288,6 @@ static
> int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
>  			IMX95_PCIE_PHY_CR_PARA_SEL,
>  			IMX95_PCIE_PHY_CR_PARA_SEL);
> 
> -	regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_PHY_GEN_CTRL,
> -			   IMX95_PCIE_REF_USE_PAD,
> -			   ext ? IMX95_PCIE_REF_USE_PAD : 0);
>  	regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_SS_RW_REG_0,
>  			   IMX95_PCIE_REF_CLKEN,
>  			   ext ? 0 : IMX95_PCIE_REF_CLKEN);
> @@ -1251,6 +1267,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
>  		pp->bridge->disable_device = imx_pcie_disable_device;
>  	}
> 
> +	if (imx_pcie->drvdata->init_pre_reset)
> +		imx_pcie->drvdata->init_pre_reset(imx_pcie);
> +
>  	imx_pcie_assert_core_reset(imx_pcie);
>  	imx_pcie_assert_perst(imx_pcie, true);
> 
> @@ -1961,6 +1980,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
>  		.core_reset = imx95_pcie_core_reset,
>  		.init_phy = imx95_pcie_init_phy,
> +		.init_pre_reset = imx95_pcie_init_pre_reset,
>  		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
>  		.enable_ref_clk = imx95_pcie_enable_ref_clk,
>  		.clr_clkreq_override = imx95_pcie_clr_clkreq_override, @@ -
> 2016,6 +2036,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.ltssm_mask = IMX95_PCIE_LTSSM_EN,
>  		.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
>  		.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> +		.init_pre_reset = imx95_pcie_init_pre_reset,
>  		.init_phy = imx95_pcie_init_phy,
>  		.core_reset = imx95_pcie_core_reset,
>  		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
> 
> base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83
> --
> 2.37.1