[PATCH] drivers: altera_edac: Fix OCRAM ECC init for warm reset

[Dinh Nguyen]

On 5/9/26 09:38, muhammad.nazim.amirul.nazle.asmade at altera.com wrote:
> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade at altera.com>
> 
> The OCRAM ECC is always enabled either by the BootROM or by the
> Secure Device Manager (SDM) during a power-on reset on SoCFPGA.
> 
> However, during a warm reset, the OCRAM content is retained to
> preserve data, while the control and status registers are reset to
> their default values. As a result, ECC must be explicitly re-enabled
> after a warm reset.
> 
> Signed-off-by: Niravkumar L Rabara <nirav.rabara at altera.com>
> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade at altera.com>
> ---
>   drivers/edac/altera_edac.c | 10 ++++++++--
>   1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
> index 103b2c2eba2a..9e6a9786a881 100644
> --- a/drivers/edac/altera_edac.c
> +++ b/drivers/edac/altera_edac.c
> @@ -1186,8 +1186,14 @@ altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
>   
>   	/* Verify OCRAM has been initialized */
>   	if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
> -			   (base + ALTR_A10_ECC_INITSTAT_OFST)))
> -		return -ENODEV;
> +			   (base + ALTR_A10_ECC_INITSTAT_OFST))) {
> +		if (!ecc_test_bits(ALTR_A10_ECC_EN,
> +				   (base + ALTR_A10_ECC_CTRL_OFST)))
> +			ecc_set_bits(ALTR_A10_ECC_EN,
> +				     (base + ALTR_A10_ECC_CTRL_OFST));
> +		else
> +			return -ENODEV;
> +	}
>   
>   	/* Enable IRQ on Single Bit Error */
>   	writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));

This patch fails to apply to both v7.1-rc1 and linux-next. Please base 
your patch to the latest and resend.

Thanks,
Dinh