[PATCH v4 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control

[Conor Dooley]

On Wed, Jun 17, 2026 at 02:04:33PM +0800, joakim.zhang at cixtech.com wrote:
> From: Joakim Zhang <joakim.zhang at cixtech.com>
> 
> The Cix Sky1 Audio Subsystem (AUDSS) groups audio-related clock, reset
> and control registers in a dedicated CRU block. Software reset lines are
> exposed on the syscon parent via #reset-cells, following the same model
> as the existing Sky1 FCH and S5 system control bindings.
> 
> A clock-controller child node is required under the audss syscon. It has
> no reg property of its own and accesses the parent register block for mux,
> divider and gate fields.
> 
> The AUDSS is also controlled by one power domain and reset part.
> 
> Signed-off-by: Joakim Zhang <joakim.zhang at cixtech.com>
> ---
>  .../soc/cix/cix,sky1-system-control.yaml      | 48 +++++++++++++++++++
>  .../reset/cix,sky1-audss-system-control.h     | 25 ++++++++++
>  2 files changed, 73 insertions(+)
>  create mode 100644 include/dt-bindings/reset/cix,sky1-audss-system-control.h
> 
> diff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml
> index a01a515222c6..5a1cd5c24ade 100644
> --- a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml
> +++ b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml
> @@ -19,6 +19,7 @@ properties:
>        - enum:
>            - cix,sky1-system-control
>            - cix,sky1-s5-system-control
> +          - cix,sky1-audss-system-control
>        - const: syscon

If the only thing these share are being a reset controller and having a
syscon fallback, I think it should be in a different file.

pw-bot: changes-requested

Cheers,
Conor.

>  
>    reg:
> @@ -27,6 +28,38 @@ properties:
>    '#reset-cells':
>      const: 1
>  
> +  power-domains:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  clock-controller:
> +    type: object
> +    properties:
> +      compatible:
> +        const: cix,sky1-audss-clock
> +    required:
> +      - compatible
> +    additionalProperties: true
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: cix,sky1-audss-system-control
> +    then:
> +      required:
> +        - clock-controller
> +        - power-domains
> +        - resets
> +    else:
> +      properties:
> +        clock-controller: false
> +        power-domains: false
> +        resets: false
> +
>  required:
>    - compatible
>    - reg
> @@ -40,3 +73,18 @@ examples:
>        reg = <0x4160000 0x100>;
>        #reset-cells = <1>;
>      };
> +  - |
> +    audss_syscon: system-controller at 7110000 {
> +        compatible = "cix,sky1-audss-system-control", "syscon";
> +        reg = <0x7110000 0x10000>;
> +        power-domains = <&smc_devpd 0>;
> +        resets = <&s5_syscon 31>;
> +        #reset-cells = <1>;
> +
> +        clock-controller {
> +            compatible = "cix,sky1-audss-clock";
> +            #clock-cells = <1>;
> +            clocks = <&scmi_clk 0>, <&scmi_clk 2>, <&scmi_clk 4>, <&scmi_clk 5>;
> +            clock-names = "x8k", "x11k", "sys", "48m";
> +        };
> +    };
> diff --git a/include/dt-bindings/reset/cix,sky1-audss-system-control.h b/include/dt-bindings/reset/cix,sky1-audss-system-control.h
> new file mode 100644
> index 000000000000..aabdce60b094
> --- /dev/null
> +++ b/include/dt-bindings/reset/cix,sky1-audss-system-control.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +/*
> + * Copyright 2026 Cix Technology Group Co., Ltd.
> + */
> +#ifndef DT_BINDING_RESET_CIX_SKY1_AUDSS_SYSTEM_CONTROL_H
> +#define DT_BINDING_RESET_CIX_SKY1_AUDSS_SYSTEM_CONTROL_H
> +
> +#define AUDSS_I2S0_SW_RST	0
> +#define AUDSS_I2S1_SW_RST	1
> +#define AUDSS_I2S2_SW_RST	2
> +#define AUDSS_I2S3_SW_RST	3
> +#define AUDSS_I2S4_SW_RST	4
> +#define AUDSS_I2S5_SW_RST	5
> +#define AUDSS_I2S6_SW_RST	6
> +#define AUDSS_I2S7_SW_RST	7
> +#define AUDSS_I2S8_SW_RST	8
> +#define AUDSS_I2S9_SW_RST	9
> +#define AUDSS_WDT_SW_RST	10
> +#define AUDSS_TIMER_SW_RST	11
> +#define AUDSS_MB0_SW_RST	12
> +#define AUDSS_MB1_SW_RST	13
> +#define AUDSS_HDA_SW_RST	14
> +#define AUDSS_DMAC_SW_RST	15
> +
> +#endif
> -- 
> 2.50.1
> 
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