[RFC PATCH 15/22] arm64: dts: ti: k3-am62p: Add DDR and controller node

[MANNURU VENKATESWARLU]

From: Santhosh Kumar K <s-k6 at ti.com>

Add DDR Controller and LPDDR4 node for AM62Px device. This defines the
memory controller with its register reginos, interrupts, power domains
and clock requirements.

Signed-off-by: Santhosh Kumar K <s-k6 at ti.com>
Signed-off-by: Gandhar Deshpande <g-deshpande at ti.com>
Signed-off-by: Neha Malcom Francis <n-francis at ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru at ti.com>
---
 .../dts/ti/k3-am62p-j722s-common-main.dtsi    | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
index f130c7cb998d7..4e07ff4fa21ea 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
@@ -1135,4 +1135,29 @@ hsm: remoteproc at 43c00000 {
 		/* reserved for early-stage bootloader */
 		status = "reserved";
 	};
+
+	memory-controller at f300000 {
+		compatible = "ti,am62p-ddrss", "ti,am62a-ddrss";
+		reg = <0x00 0x0f300000 0x00 0x200>;
+		reg-names = "ss_cfg";
+		ranges = <0x00 0x00 0x00 0x0f308000 0x00 0x5e10>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 170 0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ddr: ddr at 0 {
+			compatible = "cdns,k3-ddr";
+			reg = <0x00 0x0000 0x00 0x6cc>,
+				<0x00 0x2000 0x00 0x6a0>,
+				<0x00 0x4000 0x00 0x1e10>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+		};
+
+		ddr_pmu0: ddr-pmu at 100 {
+			compatible = "ti,k3-ddr-pmu";
+			reg = <0x00 0x100 0x00 0x14>;
+		};
+	};
 };
-- 
2.34.1