[RFC PATCH 16/22] arm64: dts: ti: k3-am64: Add DDR and controller node

[MANNURU VENKATESWARLU]

From: Neha Malcom Francis <n-francis at ti.com>

Add DDR Controller and LPDDR4 node for AM64x device. This defines the
memory controller with its register regions, interrupts, power domains
and clock requirements.

Signed-off-by: Neha Malcom Francis <n-francis at ti.com>
Signed-off-by: Gandhar Deshpande <g-deshpande at ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru at ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 33 ++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 1b1d3970888b8..f7a331ed00e28 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1675,4 +1675,37 @@ main_vtm0: temperature-sensor at b00000 {
 		power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
 		#thermal-sensor-cells = <1>;
 	};
+
+	memorycontroller: memorycontroller at f300000 {
+		compatible = "ti,am64-ddrss";
+		reg = <0x00 0x0f308000 0x00 0x4000>,
+		      <0x00 0x43014000 0x00 0x100>,
+		      <0x00 0x0f300000 0x00 0x200>;
+		reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+		power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
+				<&k3_pds 55 TI_SCI_PD_SHARED>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x0000 0x00 0x0f308000 0x00 0x55f8>;
+		ti,ddr-freq1   = <0>;
+		ti,ddr-freq2   = <0>;
+		ti,ddr-fhs-cnt = <0>;
+		clocks = <&k3_clks 138 0>, <&k3_clks 16 4>;
+		bootph-pre-ram;
+
+		ddr: ddr at 0 {
+			compatible = "cdns,k3-ddr";
+			reg = <0x00 0x0000 0x00 0x69c>,
+			      <0x00 0x2000 0x00 0x564>,
+			      <0x00 0x4000 0x00 0x15f8>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+			bootph-pre-ram;
+		};
+
+		ddr_pmu0: ddr-pmu at 100 {
+			compatible = "ti,k3-ddr-pmu";
+			reg = <0x00 0x100 0x00 0x14>;
+		};
+	};
 };
-- 
2.34.1