[PATCH v2 5/8] iommu/arm-smmu-v3: Precompute the invalidation commands
Jason Gunthorpe
jgg at nvidia.com
Wed Jul 8 06:15:53 PDT 2026
On Wed, Jul 08, 2026 at 09:00:50AM +0000, Mostafa Saleh wrote:
> On Tue, Jul 07, 2026 at 11:58:12AM -0300, Jason Gunthorpe wrote:
> > On Tue, Jul 07, 2026 at 11:52:25AM +0000, Mostafa Saleh wrote:
> > > On Mon, Jul 06, 2026 at 01:26:42PM -0300, Jason Gunthorpe wrote:
> > > > Store the required cmd data in the tlbi and just copy it out when
> > > > processing each item in the invs list. The cmd form only depends on
> > > > if the instance supports RIL or not, otherwise it is always the same.
> > > >
> > > > This avoids redundant calculations for each invs entry.
> > >
> > > I do not understand how does this avoids redundant calculation?
> > > This would be the case if the domain shares multiple SMMUs,
> > > otherwise, a range TLB invalidation should be unique and can not be
> > > reused.
> >
> > Right, if there are multiple SMMUs for the domain then currently it
> > recomputes the range for every one.
> >
> > At the moment I think we can't have multiple SMMUs per domain but
> > Nioclin has a patch series changing that
>
> Yes, it is not possible at the moment, I think it makes sense to have
> it in this series, but a comment would be helpful as it is not clear
> from just reading the code.
>
> However, as I mentioned I am not sure if that actually helps on a real
> system, is that something that you noticed during perf or based on the
> code?
Not measured, it just fell out of how the tlbi flow ended up being
structured.
Jason
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