[PATCH v2 5/8] iommu/arm-smmu-v3: Precompute the invalidation commands

Nicolin Chen nicolinc at nvidia.com
Tue Jul 7 13:31:53 PDT 2026


On Mon, Jul 06, 2026 at 01:26:42PM -0300, Jason Gunthorpe wrote:
> @@ -2471,10 +2451,13 @@ static bool arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu,
>  	if (num_tg == 1) {
>  		if (!ttl)
>  			ttl = 3;
> -		arm_smmu_cmdq_batch_add_ril(smmu, cmds, cmd, tlbi->leaf_only,
> -					    cur_tg << tg_lg2, 0, 0, ttl,
> -					    tg_enc);
> -		return true;
> +		tlbi->range.data0 = 0;
> +		tlbi->range.data1 =
> +			FIELD_PREP(CMDQ_TLBI_1_LEAF, tlbi->leaf_only) |
> +			FIELD_PREP(CMDQ_TLBI_1_TTL, ttl) |
> +			FIELD_PREP(CMDQ_TLBI_1_TG, tg_enc) |
> +			(cur_tg << tg_lg2);
> +		return;
>  	}
[...]
> +	tlbi->range.data0 =
> +		FIELD_PREP(CMDQ_TLBI_0_NUM,
> +			   DIV_ROUND_UP_ULL(num_tg, 1ULL << scale) - 1) |
> +		FIELD_PREP(CMDQ_TLBI_0_SCALE, scale);
> +	tlbi->range.data1 = FIELD_PREP(CMDQ_TLBI_1_LEAF, tlbi->leaf_only) |
> +			    FIELD_PREP(CMDQ_TLBI_1_TTL, ttl) |
> +			    FIELD_PREP(CMDQ_TLBI_1_TG, tg_enc) |
> +			    (cur_tg << tg_lg2);

Could this be slightly cleaner:

	unsigned int num = 0, scale = 0;
	...
	if (num_tg == 1) {
		if (!ttl)
			ttl = 3;
		goto build;
	}

	scale = fls64((num_tg - 1) / 32);
	num = DIV_ROUND_UP_ULL(num_tg, 1ULL << scale) - 1;
build:
	tlbi->range.data0 = FIELD_PREP(CMDQ_TLBI_0_NUM, num) |
			    FIELD_PREP(CMDQ_TLBI_0_SCALE, scale);
	tlbi->range.data1 = FIELD_PREP(CMDQ_TLBI_1_LEAF, tlbi->leaf_only) |
			    FIELD_PREP(CMDQ_TLBI_1_TTL, ttl) |
			    FIELD_PREP(CMDQ_TLBI_1_TG, tg_enc) |
			    (cur_tg << tg_lg2);

?

> @@ -2711,6 +2711,14 @@ void arm_smmu_domain_inv_range(struct arm_smmu_domain *smmu_domain,
>  	rcu_read_lock();
>  	invs = rcu_dereference(smmu_domain->invs);
>  
> +	/* Only precaculate RIL if it will be used. */

precalculate

> +	if (invs->has_range_inv) {
> +		if (!tlbi.range.use_full_inv)
> +			arm_smmu_tlbi_calc_range(&tlbi);
> +	} else {
> +		tlbi.range.use_full_inv = true;

I am a bit unsure about this line since invs has no RIL entry.

Is it set for a defensive reason?

Nicolin



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