[PATCH 3/3] arm64: Sort registers in cpu-feature-registers.rst

[Catalin Marinas]

On Fri, May 22, 2026 at 06:58:39PM +0100, Mark Brown wrote:
> -  ID_AA64PFR0_EL1 - Processor Feature Register 0
> +  ID_AA64ISAR1_EL1 - Instruction set attribute register 1
>  
>       +------------------------------+---------+---------+
>       | Name                         |  bits   | visible |
>       +------------------------------+---------+---------+
> -     | DIT                          | [51-48] |    y    |
> +     | LS64                         | [63-60] |    y    |
>       +------------------------------+---------+---------+
> -     | MPAM                         | [43-40] |    n    |
> +     | I8MM                         | [55-52] |    y    |
>       +------------------------------+---------+---------+
> -     | SVE                          | [35-32] |    y    |
> +     | DGH                          | [51-48] |    y    |
>       +------------------------------+---------+---------+
> -     | GIC                          | [27-24] |    n    |
> +     | BF16                         | [47-44] |    y    |
>       +------------------------------+---------+---------+
> -     | AdvSIMD                      | [23-20] |    y    |
> +     | SB                           | [39-36] |    y    |
>       +------------------------------+---------+---------+
> -     | FP                           | [19-16] |    y    |
> +     | FRINTTS                      | [35-32] |    y    |
>       +------------------------------+---------+---------+
> -     | EL3                          | [15-12] |    n    |
> +     | GPI                          | [31-28] |    y    |
>       +------------------------------+---------+---------+
> -     | EL2                          | [11-8]  |    n    |
> +     | GPA                          | [27-24] |    y    |
>       +------------------------------+---------+---------+
> -     | EL1                          | [7-4]   |    n    |
> +     | LRCPC                        | [23-20] |    y    |
>       +------------------------------+---------+---------+
> -     | EL0                          | [3-0]   |    n    |
> +     | FCMA                         | [19-16] |    y    |
> +     +------------------------------+---------+---------+
> +     | JSCVT                        | [15-12] |    y    |
> +     +------------------------------+---------+---------+
> +     | API                          | [11-8]  |    y    |
> +     +------------------------------+---------+---------+
> +     | APA                          | [7-4]   |    y    |
> +     +------------------------------+---------+---------+
> +     | DPB                          | [3-0]   |    y    |
>       +------------------------------+---------+---------+

The patch is fine but I just realised that we are really inconsistent
with the non-visible things. We exposed a few hear, I guess in the early
days, and then we stopped, just adding the occasional visible fields.

Shall we drop the 'visible' column altogether and only document the
visible fields here?

-- 
Catalin