[PATCH 2/3] arm64: Document missing bitfields in cpu-feature-registers.rst

[Catalin Marinas]

On Fri, May 22, 2026 at 06:58:38PM +0100, Mark Brown wrote:
> --- a/Documentation/arch/arm64/cpu-feature-registers.rst
> +++ b/Documentation/arch/arm64/cpu-feature-registers.rst
> @@ -113,6 +113,30 @@ infrastructure:
>  4. List of registers with visible features
>  -------------------------------------------
>  
> +  ID_AA6FPFR0_EL1 - Floating Point feature ID register 0

That's missing a '4' in '64'.

> +  ID_AA6SMFR0_EL1 - SME feature ID register 0

Same here.

-- 
Catalin