[PATCH 2/2] perf: arm_spe: Prefer large AUX mappings

[Leo Yan]

Commit 18049c8cff9c ("perf/aux: Allocate non-contiguous AUX pages by
default") made the AUX allocator use order-0 pages by default unless a
PMU explicitly asks for contiguous allocations.

SPE writes trace data to the AUX buffer via virtual addresses and relies
on page-table translation. When a large AUX buffer is allocated with
order-0, the buffer is mapped with many small mappings, increasing TLB
pressure from the trace unit itself. This can add translation latency
while collecting trace.

Set PERF_PMU_CAP_AUX_PREFER_LARGE for Arm SPE. This lets the generic AUX
allocator try larger-order chunks first, which can then be mapped by
vmap() with larger granules when the mm large-mapping support is present.

With the mm large-mapping series already applied, dd memory copy test
using a 512MB AUX buffer with SPE showed the following results over 10
iterations:

  l1d_tlb_refill: 15,921.9 -> 15,933.6  (+0.07%)
  l2d_tlb_refill: 4,285.0 -> 2,796.5  (-34.74%)
  dtlb_walk: 1,760.2 -> 1,387.9  (-21.15%)

The main improvement is the lower L2 data TLB refill count, with fewer data
TLB walks as well.

Signed-off-by: Leo Yan <leo.yan at arm.com>
---
 drivers/perf/arm_spe_pmu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
index dbd0da1116390f71edf47c93db2f6fa3b36739d1..02389d3842216d55cd06e9174d2d27ade9a2ce4b 100644
--- a/drivers/perf/arm_spe_pmu.c
+++ b/drivers/perf/arm_spe_pmu.c
@@ -1064,7 +1064,8 @@ static int arm_spe_pmu_perf_init(struct arm_spe_pmu *spe_pmu)
 	spe_pmu->pmu = (struct pmu) {
 		.module = THIS_MODULE,
 		.parent		= &spe_pmu->pdev->dev,
-		.capabilities	= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE,
+		.capabilities	= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE |
+				  PERF_PMU_CAP_AUX_PREFER_LARGE,
 		.attr_groups	= arm_spe_pmu_attr_groups,
 		/*
 		 * We hitch a ride on the software context here, so that

-- 
2.34.1