[PATCH 01/20] dt-bindings: net: add Xilinx TSN Endpoint Ethernet MAC
Nagadheeraj Rottela
nagadheeraj.rottela at amd.com
Fri Aug 7 03:44:12 PDT 2026
From: Srinivas Neeli <srinivas.neeli at amd.com>
Add a binding for the Xilinx TSN Endpoint Ethernet MAC IP. The
top-level node describes the IP wrapper, which owns the six shared
IP clocks and the xlnx,num-priorities parameter, and has two
children:
- xlnx,tsn-ep-mac: the endpoint MAC, owning the host-side DMA
channels (dmas / dma-names / tx-queues-config).
- xlnx,tsn-switch: the three-port Ethernet switch covering the
switch fabric and the two per-MAC register windows. The MDIO
controllers and PTP register blocks sit at fixed offsets inside
the per-MAC windows, accessed through the mdio-mac1 / mdio-mac2
children and per-MAC interrupt-names entries. Each external
port at N references its PHY through a phy-handle in the matching
mdio-mac<N> child.
Signed-off-by: Srinivas Neeli <srinivas.neeli at amd.com>
Co-developed-by: Nagadheeraj Rottela <nagadheeraj.rottela at amd.com>
Signed-off-by: Nagadheeraj Rottela <nagadheeraj.rottela at amd.com>
---
.../net/xlnx,tsn-endpoint-ethernet-mac.yaml | 343 ++++++++++++++++++
MAINTAINERS | 7 +
2 files changed, 350 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethernet-mac.yaml
diff --git a/Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethernet-mac.yaml b/Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethernet-mac.yaml
new file mode 100644
index 000000000000..00f52b7b623c
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethernet-mac.yaml
@@ -0,0 +1,343 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/xlnx,tsn-endpoint-ethernet-mac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx TSN Endpoint Ethernet MAC
+
+description:
+ TSN Endpoint Ethernet MAC IP implements IEEE 802.1 Time-Sensitive
+ Networking (TSN) standards and provides low-latency network connectivity
+ in either Endpoint-only or Bridged Endpoint configurations. In the
+ Bridged Endpoint mode, the IP integrates a three-port switch, with two
+ ports connected to the external network and one port connected to an
+ internal endpoint. It also supports GMII/RGMII interfaces for connection
+ to an external PHY, enabling full-duplex operation at 100 Mb/s and
+ 1 Gb/s speeds.
+
+maintainers:
+ - Srinivas Neeli <srinivas.neeli at amd.com>
+ - Nagadheeraj Rottela <nagadheeraj.rottela at amd.com>
+
+properties:
+ compatible:
+ const: xlnx,tsn-endpoint-ethernet-mac-3.0
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: GTX clock for transmitter logic and RTC
+ - description: GTX 90-degree phase shifted clock for RGMII
+ - description: Host RX FIFO clock
+ - description: Host TX FIFO clock
+ - description: Reference clock for IDELAY control
+ - description: AXI-Lite register interface clock
+
+ clock-names:
+ items:
+ - const: gtx
+ - const: gtx90
+ - const: host_rxfifo
+ - const: host_txfifo
+ - const: ref
+ - const: s_axi
+
+ ranges: true
+
+ xlnx,num-priorities:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 2
+ maximum: 8
+ description:
+ Number of traffic classes (priorities) configured in the IP.
+ This is an IP configuration parameter that determines the number of
+ priority queues available for QoS scheduling. Traffic classes map to
+ IEEE 802.1Q priority levels (0-7).
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+patternProperties:
+ "^ep-mac@":
+ type: object
+ $ref: /schemas/net/ethernet-controller.yaml#
+ description:
+ Endpoint MAC sub-node. Provides the host-side data path through the
+ DMA channels described by its dmas / dma-names.
+ properties:
+ compatible:
+ const: xlnx,tsn-ep-mac
+
+ reg:
+ maxItems: 1
+
+ dmas:
+ minItems: 2
+ maxItems: 32
+
+ dma-names:
+ minItems: 2
+ maxItems: 32
+ items:
+ pattern: "^(tx|rx)_chan(1[0-5]|[0-9])$"
+ description: |
+ Names matching the entries in 'dmas', one per DMA channel and in
+ the same order. TX channel names use "tx_chan<N>" and RX channel
+ names use "rx_chan<N>", where N is 0..15. Example: "tx_chan0",
+ "tx_chan1", ..., "rx_chan0", "rx_chan1", ....
+
+ tx-queues-config:
+ type: object
+ description:
+ TX queue configuration node that maps IP priority queues to
+ DMA TX channels. The TSN IP supports multiple priority queues for
+ QoS scheduling, and each queue can be connected to a specific DMA
+ channel. This mapping defines which DMA TX channel is used to
+ transmit packets for each priority queue. For example, queue0
+ with xlnx,dma-channel-num set to 5 means priority queue 0 uses
+ tx_chan5 for data transfer.
+
+ patternProperties:
+ "^queue[0-7]$":
+ description:
+ Each subnode represents a priority queue. The
+ xlnx,dma-channel-num property specifies which DMA TX channel
+ (tx_chan0 to tx_chan15) is connected to this queue for
+ transmitting packets.
+ type: object
+ properties:
+ xlnx,dma-channel-num:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ DMA TX channel number connected to this priority queue.
+ minimum: 0
+ maximum: 15
+
+ required:
+ - xlnx,dma-channel-num
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+ required:
+ - compatible
+ - reg
+ - dmas
+ - dma-names
+ - tx-queues-config
+
+ unevaluatedProperties: false
+
+ "^switch@":
+ type: object
+ $ref: /schemas/net/dsa/dsa.yaml#/$defs/ethernet-ports
+ description:
+ Three-port Ethernet switch sub-node. Contains the switch fabric
+ register window and the two per-MAC register windows; each per-MAC
+ window houses an MDIO controller and a PTP register block at fixed
+ offsets. The IP's per-MAC and PTP-timer interrupts are exposed here.
+
+ properties:
+ compatible:
+ const: xlnx,tsn-switch
+
+ reg:
+ items:
+ - description: Switch fabric register window
+ - description: MAC1 register window (includes MDIO and PTP)
+ - description: MAC2 register window (includes MDIO and PTP)
+
+ reg-names:
+ items:
+ - const: switch
+ - const: mac1
+ - const: mac2
+
+ interrupts:
+ maxItems: 7
+
+ interrupt-names:
+ items:
+ - const: ptp_rx_mac1
+ - const: ptp_tx_mac1
+ - const: mac_irq_mac1
+ - const: ptp_timer
+ - const: ptp_rx_mac2
+ - const: ptp_tx_mac2
+ - const: mac_irq_mac2
+
+ mdio-mac1:
+ $ref: /schemas/net/mdio.yaml#
+ description:
+ MDIO bus controller for MAC1. Registers reside inside the mac1
+ reg-names window.
+ unevaluatedProperties: false
+
+ mdio-mac2:
+ $ref: /schemas/net/mdio.yaml#
+ description:
+ MDIO bus controller for MAC2. Registers reside inside the mac2
+ reg-names window.
+ unevaluatedProperties: false
+
+ ethernet-ports:
+ type: object
+ additionalProperties: true
+
+ properties:
+ port at 0:
+ type: object
+ additionalProperties: true
+ description:
+ CPU port. Wired internally to the ep-mac sibling.
+
+ properties:
+ reg:
+ const: 0
+
+ phy-mode:
+ const: internal
+
+ patternProperties:
+ "^port@[1-2]$":
+ type: object
+ additionalProperties: true
+ description:
+ External Ethernet port (port at 1 is wired to MAC1, port at 2 to
+ MAC2). Its PHY is reached through the corresponding
+ mdio-mac<N> bus.
+
+ properties:
+ phy-mode:
+ enum:
+ - gmii
+ - rgmii
+ - rgmii-id
+
+ required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+
+ unevaluatedProperties: false
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - xlnx,num-priorities
+ - ranges
+ - '#address-cells'
+ - '#size-cells'
+
+examples:
+ - |
+ tsn_ip: tsn at 80040000 {
+ compatible = "xlnx,tsn-endpoint-ethernet-mac-3.0";
+ reg = <0x80040000 0x40000>;
+ clocks = <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_1>, <&misc_clk_1>,
+ <&misc_clk_3>, <&misc_clk_0>;
+ clock-names = "gtx", "gtx90", "host_rxfifo", "host_txfifo",
+ "ref", "s_axi";
+ xlnx,num-priorities = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80040000 0x40000>;
+
+ ep_mac: ep-mac at 16000 {
+ compatible = "xlnx,tsn-ep-mac";
+ reg = <0x16000 0xa000>;
+ dmas = <&axi_mcdma_0 0>, <&axi_mcdma_0 1>, <&axi_mcdma_0 2>,
+ <&axi_mcdma_0 3>, <&axi_mcdma_0 4>, <&axi_mcdma_0 5>,
+ <&axi_mcdma_0 6>, <&axi_mcdma_0 7>, <&axi_mcdma_0 16>,
+ <&axi_mcdma_0 17>, <&axi_mcdma_0 18>, <&axi_mcdma_0 19>,
+ <&axi_mcdma_0 20>, <&axi_mcdma_0 21>, <&axi_mcdma_0 22>,
+ <&axi_mcdma_0 23>;
+ dma-names = "tx_chan0", "tx_chan1", "tx_chan2", "tx_chan3",
+ "tx_chan4", "tx_chan5", "tx_chan6", "tx_chan7",
+ "rx_chan0", "rx_chan1", "rx_chan2", "rx_chan3",
+ "rx_chan4", "rx_chan5", "rx_chan6", "rx_chan7";
+ tx-queues-config {
+ queue0 { xlnx,dma-channel-num = <0x7>; };
+ queue1 { xlnx,dma-channel-num = <0x6>; };
+ queue2 { xlnx,dma-channel-num = <0x5>; };
+ queue3 { xlnx,dma-channel-num = <0x4>; };
+ queue4 { xlnx,dma-channel-num = <0x3>; };
+ queue5 { xlnx,dma-channel-num = <0x2>; };
+ queue6 { xlnx,dma-channel-num = <0x1>; };
+ queue7 { xlnx,dma-channel-num = <0x0>; };
+ };
+ };
+
+ tsn_switch: switch at 38000 {
+ compatible = "xlnx,tsn-switch";
+ reg = <0x38000 0x8000>,
+ <0x00000 0x14000>,
+ <0x20000 0x14000>;
+ reg-names = "switch", "mac1", "mac2";
+
+ interrupt-parent = <&intc>;
+ interrupts = <0 2>, <2 2>, <4 2>, <6 2>,
+ <1 2>, <3 2>, <5 2>;
+ interrupt-names = "ptp_rx_mac1", "ptp_tx_mac1",
+ "mac_irq_mac1", "ptp_timer",
+ "ptp_rx_mac2", "ptp_tx_mac2",
+ "mac_irq_mac2";
+
+ mdio-mac1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+ };
+
+ mdio-mac2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ };
+ };
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ethernet = <&ep_mac>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+
+ port at 2 {
+ reg = <2>;
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ };
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 08e43bc09735..ba41c224dd02 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -29607,6 +29607,13 @@ M: Harsh Jain <h.jain at amd.com>
S: Maintained
F: drivers/char/hw_random/xilinx-trng.c
+XILINX TSN ENDPOINT ETHERNET MAC DRIVER
+M: Nagadheeraj Rottela <nagadheeraj.rottela at amd.com>
+M: Srinivas Neeli <srinivas.neeli at amd.com>
+L: netdev at vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethernet-mac.yaml
+
XILINX UARTLITE SERIAL DRIVER
M: Peter Korsgaard <jacmet at sunsite.dk>
L: linux-serial at vger.kernel.org
--
2.34.1
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