[PATCH 00/20] xilinx: tsn: Add TSN Endpoint Ethernet MAC driver support
Nagadheeraj Rottela
nagadheeraj.rottela at amd.com
Fri Aug 7 03:44:11 PDT 2026
Introduce a new network driver for the AMD LogiCORE 100M/1G TSN
Subsystem IP, also known as the TSN Endpoint Ethernet MAC IP, which
implements IEEE 802.1 Time-Sensitive Networking (TSN) features for
deterministic and low-latency Ethernet communication in real-time and
industrial automation use cases.
IP Core Overview:
The AMD LogiCORE 100M/1G TSN Subsystem IP solution (named as TSN Endpoint
Ethernet MAC IP in the IP catalog) implements IEEE 802.1 Time Sensitive
Networking (TSN) Standards and provides a low latency Bridged Endpoint or
Endpoint only solutions. The bridged endpoint solution consists of a 3-port
switch that connects to an endpoint including Linux software drivers. For
Bridged Endpoint (Switch Endpoint), two ports connects to the network and
one port connects to an internal Endpoint. It supports the use of
GMII/RGMII interfaces connecting to a physical-side interface (PHY) chip
with full duplex 100 Mb/s and 1 Gb/s operations.
Features:
- IP Customizable to generate TSN Endpoint or Bridged Endpoint solution
- Supports interface to network software stack
- Designed to comply with the following IEEE standards
- 802.1AS : Precision Time Protocol (PTP) synchronization
- 802.1Qav : Credit-Based Shaper for traffic shaping
- 802.1Qbv : Time-Aware Shaper for scheduled traffic
- 802.1Qbu : Frame Preemption for ultra-low latency
- 802.1CB : Frame Replication and Elimination for redundancy
- 802.1Qcc : Stream Reservation Protocol (SRP)
- IP is customizable to enable various TSN feature-sets
- Supports 2 to 8 priority queues for scheduled, reserved (IEEE 802.1 Qav
Credit Based Shaper) and best effort traffic classes
- Provides feature rich Ethernet Switch that caters to various network
needs
* 3-port Switch (2-external, 1-internal)
* Programmable cut-through and store-forward operations
* 4-port Switch (2-external, 2-internal) extension through
'Endpoint Extension' and 'Endpoint Packet Switching' features
- Solution validated on ZCU102 & ZC702 AMD Evaluation boards.
Sample hardware architecture diagram for Bidge End Point like below:
+------------------+
| MCDMA |
+---------+--------+
Q0---Q7
|
+------------------------------------------------------------ +
| | TSN sub system(Bridge End Point) |
| | |
| +------+----+ Port 0 +-----------------------+ |
| | EndPoint |<--------->| TSN Switch | |
| | (EP) | +----+-------------+----+ |
| +-----------+ | | |
| | | |
| Port 1 Port 2 |
| | | |
| +-----------+ +-----------+ |
| | MAC-1 | | MAC-2 | |
| | (ETH1) | | (ETH2) | |
| +-----+-----+ +-----+-----+ |
| | | |
| | | |
+-------------------------------------------------------------+
| |
RGMII RGMII
| |
+-----------+ +-----------+
| PHY1 | | PHY2 |
| (Port 0) | | (Port 2) |
+-----------+ +-----------+
Software Driver Overview:
The switch-facing part of the IP is exposed through the Distributed
Switch Architecture (DSA) framework, so MAC1 and MAC2 show up to Linux
as proper switch ports (swp1, swp2) that can be enslaved to a Linux
bridge, with the endpoint acting as the CPU/conduit port. The driver
is split into a thin wrapper, an endpoint driver, a DSA switch driver,
and a DSA tag protocol, mirroring the hardware blocks:
Wrapper driver:
- Binds the top-level IP node, acquires and enables the IP-block
clocks.
- Spawns the endpoint and switch blocks as child platform devices via
devm_of_platform_populate() and carries no netdev or register access
of its own.
Endpoint driver:
- Implements the conduit net_device that Linux DMA traffic flows
through on its way to and from the switch fabric.
- Manages multi-queue TX and RX descriptor rings using the dmaengine
framework for high-performance packet transfer.
- Classifies each received frame by the source-port id carried in the
RX descriptor and attaches DSA port metadata so the DSA core can
demux it to the right user port netdev.
DSA switch driver:
- Registers a struct dsa_switch with three ports (CPU + MAC1 + MAC2)
and owns the switch fabric registers, the per-MAC register windows,
and all switch IRQs.
- Implements port_stp_state_set to drive the hardware's per-port
Disabled/Blocking/Forwarding state machine from the bridge's STP
state.
- Offloads the bridge's FDB and VLAN membership into the switch's CAM
and per-port VLAN tables (port_fdb_add/del, port_vlan_add/del), and
installs CAM trap entries so link-local STP/LLDP frames reach the
CPU port.
- Enables the bridge's TX forwarding offload so data frames take the
switch's own CAM/VLAN lookup, the same path a frame ingressing on
MAC1/MAC2 takes, instead of being flooded by software.
- Registers a per-MAC MDIO bus and wires up phylink for each port,
including PHY connection management on link state changes.
- Registers a PTP Hardware Clock (PHC) backed by the IP's shared RTC
timer block and drives the per-MAC PTP TX/RX hardware paths so
event-frame timestamping bypasses the switch fabric and DMA
entirely.
DSA tag protocol:
- Adds DSA_TAG_PROTO_XLNX_TSN. The xmit hook intercepts PTP frames for
the per-MAC PTP TX path, other frames pass through unchanged. The rcv
hook is a defensive no-op since RX demux is handled by the endpoint
driver's port metadata rather than by an in-band tag.
Changes in v1:
- Reworked the switch side of the driver onto the DSA framework
instead of exposing MAC1/MAC2 as independent, framework-unaware
netdevs.
- Added the DSA tag protocol and moved RX classification from an
skb->dev based scheme into DSA port metadata attached by the
endpoint driver.
- Added STP state offload (port_stp_state_set), bridge FDB/VLAN
offload backed by the switch CAM and VLAN tables, bridge TX
forwarding offload, and CAM trap entries for link-local control
frames.
- Carried phylink, per-MAC MDIO, and PTP support over from the
previous posting, now wired up through DSA port ops instead of
the platform driver.
- Split the driver into a thin wrapper, endpoint driver, and DSA
switch driver along the DSA compatible/binding boundaries instead
of a single flat driver.
Test information:
- Validated these changes on the net-next branch with the MCDMA patches
cherry-picked from linux-next, along with the series listed below
https://lore.kernel.org/all/20260713072146.45269-1-srinivas.neeli@amd.com/
- Performed ping, iperf3, and 2-step PTP tests on the ZynqMP platform,
including bridging swp1/swp2 through a Linux bridge with hardware
FDB/VLAN offload enabled.
Nagadheeraj Rottela (13):
net: xilinx: tsn: deliver endpoint RX frames to DSA user ports
net: dsa: tag_xlnx_tsn: add skeleton tag protocol
net: dsa: xilinx: add skeleton driver for TSN switch
net: dsa: xilinx: implement port_stp_state_set
net: dsa: xilinx: register per-MAC MDIO buses
net: dsa: xilinx: wire up phylink for the switch ports
net: dsa: xilinx: program MAC frame filter and per-port nibbles
net: dsa: xilinx: register PHC backed by the RTC timer block
net: dsa: xilinx: drive per-MAC PTP TX/RX hardware paths
net: dsa: xilinx: opt into TX forwarding offload on bridge join
net: dsa: xilinx: offload the bridge FDB to the switch CAM
net: dsa: xilinx: offload bridge VLAN filtering to the switch
net: dsa: xilinx: trap link-local control frames to the CPU port
Srinivas Neeli (7):
dt-bindings: net: add Xilinx TSN Endpoint Ethernet MAC
net: xilinx: tsn: add TSN endpoint wrapper driver
net: xilinx: tsn: add endpoint MAC driver skeleton
net: xilinx: tsn: parse endpoint DMA channel configuration
net: xilinx: tsn: bring up the endpoint MCDMA channels
net: xilinx: tsn: add the endpoint RX data path
net: xilinx: tsn: add the endpoint TX data path
.../net/xlnx,tsn-endpoint-ethernet-mac.yaml | 343 ++++
MAINTAINERS | 11 +
drivers/net/dsa/Kconfig | 2 +
drivers/net/dsa/Makefile | 1 +
drivers/net/dsa/xilinx/Kconfig | 12 +
drivers/net/dsa/xilinx/Makefile | 3 +
drivers/net/dsa/xilinx/xilinx_tsn.c | 1621 +++++++++++++++++
drivers/net/dsa/xilinx/xilinx_tsn.h | 417 +++++
drivers/net/dsa/xilinx/xilinx_tsn_ptp.c | 590 ++++++
drivers/net/ethernet/xilinx/Kconfig | 1 +
drivers/net/ethernet/xilinx/Makefile | 1 +
drivers/net/ethernet/xilinx/tsn/Kconfig | 16 +
drivers/net/ethernet/xilinx/tsn/Makefile | 2 +
drivers/net/ethernet/xilinx/tsn/xilinx_tsn.h | 15 +
.../net/ethernet/xilinx/tsn/xilinx_tsn_ep.c | 926 ++++++++++
.../net/ethernet/xilinx/tsn/xilinx_tsn_main.c | 108 ++
include/linux/dsa/xlnx_tsn.h | 25 +
include/net/dsa.h | 2 +
net/dsa/Kconfig | 9 +
net/dsa/Makefile | 1 +
net/dsa/tag_xlnx_tsn.c | 60 +
21 files changed, 4166 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/xlnx,tsn-endpoint-ethernet-mac.yaml
create mode 100644 drivers/net/dsa/xilinx/Kconfig
create mode 100644 drivers/net/dsa/xilinx/Makefile
create mode 100644 drivers/net/dsa/xilinx/xilinx_tsn.c
create mode 100644 drivers/net/dsa/xilinx/xilinx_tsn.h
create mode 100644 drivers/net/dsa/xilinx/xilinx_tsn_ptp.c
create mode 100644 drivers/net/ethernet/xilinx/tsn/Kconfig
create mode 100644 drivers/net/ethernet/xilinx/tsn/Makefile
create mode 100644 drivers/net/ethernet/xilinx/tsn/xilinx_tsn.h
create mode 100644 drivers/net/ethernet/xilinx/tsn/xilinx_tsn_ep.c
create mode 100644 drivers/net/ethernet/xilinx/tsn/xilinx_tsn_main.c
create mode 100644 include/linux/dsa/xlnx_tsn.h
create mode 100644 net/dsa/tag_xlnx_tsn.c
--
2.34.1
More information about the linux-arm-kernel
mailing list