[PATCH] iommu/arm-smmu-v3: Allow disabling Stage 1 translation

Evangelos Petrongonas epetron at amazon.de
Tue Apr 21 23:44:31 PDT 2026


On Mon, Apr 20, 2026 at 09:40:32AM -0300 Jason Gunthorpe wrote:
> On Mon, Apr 20, 2026 at 12:32:01PM +0000, Evangelos Petrongonas wrote:
> > When the hardware advertises both Stage 1 and Stage 2 translation, the
> > driver prefers Stage 1 for DMA domain allocation and only falls back to
> > Stage 2 if Stage 1 is not supported.
> > 
> > Some configurations may want to force Stage 2 translation even when the
> > hardware supports Stage 1. 
> 
> Why? You really need to explain why for a patch like this.
> 
> If there really is some HW issue I think it is more appropriate to get
> an IORT flag or IDR detection that the HW has a problem.

It's not a hardware bug there's no IORT or IDR bit that would make sense
here.

The motivation is live update of the hypervisor: we want to kexec into a
new kernel while keeping DMA from passthrough devices flowing, which
means the SMMU's translation state has to survive the handover. The Live
Update Orchestrator work [1] and the in-progress  "iommu: Add live
update state preservation" series [2] are building exactly this plumbing
on top of KHO; [2]'s cover letter calls out Arm SMMUv3 support as future
work, and an earlier RFC from Amazon [3] sketched the same idea for
iommufd.

For this use case, Stage 2 is materially easier to persist than Stage 1,
for structural rather than performance reasons: An S2 STE carries the
whole translation configuration inline. To hand over an S2 domain, the
pre-kexec kernel only needs to preserve the stream table pages and the
S2 pgtable pages. An S1 STE points at a Context Descriptor table and as
a result Persisting S1 therefore requires preserving the CD table pages
too, and because the CD is keyed by ASID coordinating ASID identity
across the handover.

In the long term the plan should be to persist both stages.
However, until a patch series that properly introduces SMMU support for
is developed/posted we would like to experiment with S1+S2-capable
hardware with an easier to implement handover machinery, that relies on
S2 translations.

[1] https://lwn.net/Articles/1021442/ — Live Update Orchestrator
[2] https://lore.kernel.org/all/20260203220948.2176157-1-skhawaja@google.com/ —
[PATCH 00/14] iommu: Add live update state preservation
[3] https://lore.kernel.org/all/20240916113102.710522-1-jgowans@amazon.com/ — [RFC
PATCH 00/13] Support iommu(fd) persistence for live update

> Jason

Kind Regards,
Evangelos



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