[PATCH] KVM: arm64: Advertise ID_AA64PFR2_EL1.GCIE

Biju Das biju.das.jz at bp.renesas.com
Sun Apr 5 05:11:49 PDT 2026


Hi Marc,

> -----Original Message-----
> From: Biju Das
> Sent: 05 April 2026 13:09
> Subject: Re: [PATCH] KVM: arm64: Advertise ID_AA64PFR2_EL1.GCIE
> 
> 
> Hi,
> 
> > Hi Marc,
> >
> > On Wed, Apr 01, 2026 at 06:00:17PM +0100, Marc Zyngier wrote:
> > > As we are missing ID_AA64PFR2_EL1.GCIE from the kernel feature set,
> > > userspace cannot write ID_AA64PFR2_EL1 with GCIE set, even if we are
> > > on a GICv5 host.
> > >
> > > Add the required field description.
> > >
> > > Signed-off-by: Marc Zyngier <maz at kernel.org>
> > > ---
> > >  arch/arm64/kernel/cpufeature.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/arch/arm64/kernel/cpufeature.c
> > > b/arch/arm64/kernel/cpufeature.c index 32c2dbcc0c641..5bca6e064ca72
> > > 100644
> > > --- a/arch/arm64/kernel/cpufeature.c
> > > +++ b/arch/arm64/kernel/cpufeature.c
> > > @@ -327,6 +327,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = {
> > >  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0),
> > >  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4,
> ID_AA64PFR2_EL1_MTEFAR_NI),
> > >  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE,
> > > ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4,
> > > ID_AA64PFR2_EL1_MTESTOREONLY_NI),
> > > +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE,
> > > +ID_AA64PFR2_EL1_GCIE_SHIFT, 4, ID_AA64PFR2_EL1_GCIE_NI),
> > >  	ARM64_FTR_END,
> > >  };
> > >
> > > --
> > > 2.47.3
> > >
> >
> > After this change in -next as commit 899ff451fcee ("KVM: arm64:
> > Advertise ID_AA64PFR2_EL1.GCIE"), I am seeing a warning on boot in my
> > simple QEMU boot tests.
> >
> >   $ make -skj"$(nproc)" ARCH=arm64 CROSS_COMPILE=aarch64-linux-
> > mrproper virtconfig Image.gz
> >
> >   $ curl -LSs
> > https://github.com/ClangBuiltLinux/boot-utils/releases/download/202411
> > 20-044434/arm64-rootfs.cpio.zst | zstd -d >rootfs.cpio
> >
> >   $ qemu-system-aarch64 \
> >       -display none \
> >       -nodefaults \
> >       -machine virt,gic-version=max \
> >       -append 'console=ttyAMA0 earlycon' \
> >       -kernel arch/arm64/boot/Image.gz \
> >       -initrd rootfs.cpio \
> >       -cpu host \
> >       -enable-kvm \
> >       -m 1G \
> >       -smp 8 \
> >       -serial mon:stdio
> >   [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x413fd0c1]
> >   [    0.000000] Linux version 7.0.0-rc4-00058-g899ff451fcee (nathan at aadp) (aarch64-linux-gcc (GCC)
> 15.2.0, GNU ld (GNU Binutils) 2.45) #1 SMP PREEMPT Sat Apr  4 06:55:05 MST 2026
> >   ...
> >   [    0.000000] ------------[ cut here ]------------
> >   [    0.000000] SYS_ID_AA64PFR2_EL1 has feature overlap at shift 12
> >   [    0.000000] WARNING: arch/arm64/kernel/cpufeature.c:986 at init_cpu_features+0xbc/0x344, CPU#0:
> swapper/0
> >   [    0.000000] Modules linked in:
> >   [    0.000000] CPU: 0 UID: 0 PID: 0 Comm: swapper Not tainted 7.0.0-rc4-00058-g899ff451fcee #1
> PREEMPT
> >   [    0.000000] Hardware name: linux,dummy-virt (DT)
> >   [    0.000000] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> >   [    0.000000] pc : init_cpu_features+0xbc/0x344
> >   [    0.000000] lr : init_cpu_features+0xbc/0x344
> >   [    0.000000] sp : ffffcd0982373db0
> >   [    0.000000] x29: ffffcd0982373db0 x28: 0000000000000010 x27: ffffcd0981c63878
> >   [    0.000000] x26: 0000000000000018 x25: ffffcd0982013f38 x24: ffffcd0981c69068
> >   [    0.000000] x23: ffffcd0981c635f0 x22: ffffcd0982388640 x21: 0000000000000003
> >   [    0.000000] x20: 0000000000000017 x19: ffffcd09824c9308 x18: 000000000000000a
> >   [    0.000000] x17: 5d305b203837205d x16: 305b203737205d30 x15: 0000000000000000
> >   [    0.000000] x14: 0000000000000000 x13: 3231207466696873 x12: 2074612070616c72
> >   [    0.000000] x11: 0000000000000058 x10: 0000000000000018 x9 : ffffcd0982396598
> >   [    0.000000] x8 : 0000000000057fa8 x7 : 000000000000002a x6 : ffffcd09823ee598
> >   [    0.000000] x5 : ffffcd09823ee598 x4 : 0000000000000000 x3 : 0000000000000000
> >   [    0.000000] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffffcd09823852c0
> >   [    0.000000] Call trace:
> >   [    0.000000]  init_cpu_features+0xbc/0x344 (P)
> >   [    0.000000]  cpuinfo_store_boot_cpu+0x48/0x54
> >   [    0.000000]  smp_prepare_boot_cpu+0x28/0x38
> >   [    0.000000]  start_kernel+0x248/0x780
> >   [    0.000000]  __primary_switched+0x88/0x90
> >   [    0.000000] ---[ end trace 0000000000000000 ]---
> >   ...
> >   ```
> >
> > Is this expected? I assume not, hence the report. If there is any
> > information I can provide or patches I can test, I am more than happy
> > to do so.
> 
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index
> 5bca6e064ca72..1bfaa96881dab 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -325,9 +325,9 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
> 
>  static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = {
>  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0),
> +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE,
> +ID_AA64PFR2_EL1_GCIE_SHIFT, 4, ID_AA64PFR2_EL1_GCIE_NI),
>  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4,
> ID_AA64PFR2_EL1_MTEFAR_NI),
>  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4,
> ID_AA64PFR2_EL1_MTESTOREONLY_NI),
> -	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_GCIE_SHIFT, 4,
> ID_AA64PFR2_EL1_GCIE_NI),
>  	ARM64_FTR_END,
>  };
> 
> The below next-20260403 warning on RZ/G3L SMARC EVK is fixed by the above code.
> 
> [    0.000000] Call trace:
> [    0.000000]  init_cpu_features+0xb8/0x2fc (P)
> [    0.000000]  cpuinfo_store_boot_cpu+0x48/0x54
> [    0.000000]  smp_prepare_boot_cpu+0x24/0x30
> [    0.000000]  start_kernel+0x230/0x6a4
> [    0.000000]  __primary_switched+0x88/0x90
> 

I just tested your patch

Tested-by: Biju Das <biju.das.jz at bp.renesas.com>

Cheers,
Biju



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