[PATCH] arm64: dts: fvp: Add ETE and TRBE nodes for Rev C model

[Leo Yan]

The FVP Rev C model includes CoreSight ETE and TRBE support.  These
features can be enabled by specifying parameters when launching the
model:

  -C cluster0.has_ete: 1
  -C cluster1.has_ete: 1
  -C cluster0.has_trbe: 1
  -C cluster1.has_trbe: 1

This change adds device tree bindings for the ETE and TRBE nodes.  They
are disabled by default to prevent kernel warnings from failed driver
probes, as the model does not enable the features unless explicitly
specified.

Signed-off-by: Leo Yan <leo.yan at arm.com>
---
 arch/arm64/boot/dts/arm/fvp-base-revc.dts | 62 +++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
index 2c2c9f45b3fe..d090badbdbd7 100644
--- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
+++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
@@ -273,6 +273,68 @@ spe-pmu {
 		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	ete0 {
+		compatible = "arm,embedded-trace-extension";
+		arm,coresight-loses-context-with-cpu;
+		cpu = <&cpu0>;
+		status = "disabled";
+	};
+
+	ete1 {
+		compatible = "arm,embedded-trace-extension";
+		arm,coresight-loses-context-with-cpu;
+		cpu = <&cpu1>;
+		status = "disabled";
+	};
+
+	ete2 {
+		compatible = "arm,embedded-trace-extension";
+		arm,coresight-loses-context-with-cpu;
+		cpu = <&cpu2>;
+		status = "disabled";
+	};
+
+	ete3 {
+		compatible = "arm,embedded-trace-extension";
+		arm,coresight-loses-context-with-cpu;
+		cpu = <&cpu3>;
+		status = "disabled";
+	};
+
+	ete4 {
+		compatible = "arm,embedded-trace-extension";
+		arm,coresight-loses-context-with-cpu;
+		cpu = <&cpu4>;
+		status = "disabled";
+	};
+
+	ete5 {
+		compatible = "arm,embedded-trace-extension";
+		arm,coresight-loses-context-with-cpu;
+		cpu = <&cpu5>;
+		status = "disabled";
+	};
+
+	ete6 {
+		compatible = "arm,embedded-trace-extension";
+		arm,coresight-loses-context-with-cpu;
+		cpu = <&cpu6>;
+		status = "disabled";
+	};
+
+	ete7 {
+		compatible = "arm,embedded-trace-extension";
+		arm,coresight-loses-context-with-cpu;
+		cpu = <&cpu7>;
+		status = "disabled";
+	};
+
+	trbe {
+		compatible = "arm,trace-buffer-extension";
+		interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_LOW>;
+		status = "disabled";
+	};
+
 	pci: pci at 40000000 {
 		#address-cells = <0x3>;
 		#size-cells = <0x2>;
-- 
2.34.1