[PATCH 3/9] drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver

[Jonathan Cameron]

On Tue, 18 Feb 2025 17:19:54 +0800
Yicong Yang <yangyicong at huawei.com> wrote:

> From: Junhao He <hejunhao3 at huawei.com>
> 
> HiSilicon DDRC v3 PMU has the different interrupt register offset
> compared to the v2. Add device information of v3 PMU with ACPI
> HID HISI0235.
> 
> Signed-off-by: Junhao He <hejunhao3 at huawei.com>
> Signed-off-by: Yicong Yang <yangyicong at hisilicon.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron at huawei.com>