[PATCH v9 01/10] clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs

[Taniya Das]

On 6/27/2025 8:39 PM, Konrad Dybcio wrote:
> On 6/25/25 12:31 PM, Taniya Das wrote:
>>
>>
>> On 6/15/2025 12:20 AM, Konrad Dybcio wrote:
>>> On 6/12/25 11:55 AM, Taniya Das wrote:
>>>> The alpha PLLs which slew to a new frequency at runtime would require
>>>> the PLL to calibrate at the mid point of the VCO. Add the new PLL ops
>>>> which can support the slewing of the PLL to a new frequency.
>>>>
>>>> Reviewed-by: Imran Shaik <quic_imrashai at quicinc.com>
>>>> Signed-off-by: Taniya Das <quic_tdas at quicinc.com>
>>>> ---
> 
> [...]
> 
>>>> +	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
>>>> +	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(a));
>>>> +	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(a));
>>>> +
>>>> +	/* Ensure that the write above goes before slewing the PLL */
>>>> +	mb();
>>>
>>> Here however, the write may not arrive at the clock controller before you
>>> proceed to slew_update()
>>>
>>
>> Yes, it is required here and will keep it.
> 
> You should change it to a readback instead
> 

Okay, I can introduce a readback, but as per the PLL code we have been
using mb() at most places. But I am okay to update it.

> Konrad