[PATCH v2 01/10] dt-bindings: soc: aspeed: Add ASPEED PCIe Config support
Krzysztof Kozlowski
krzk at kernel.org
Wed Jul 16 01:24:27 PDT 2025
On Tue, Jul 15, 2025 at 11:43:11AM +0800, Jacky Chou wrote:
> +maintainers:
> + - Jacky Chou <jacky_chou at aspeedtech.com>
> +
> +description: |
Drop |
> + The ASPEED PCIe configuration syscon block provides a set of registers shared
> + by multiple PCIe-related devices within the SoC. This node represents the
> + common configuration space that allows these devices to coordinate and manage
> + shared PCIe settings, including address mapping, control, and status
> + registers. The syscon interface enables for various PCIe devices to access
> + and modify these shared registers in a consistent and centralized manner.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,pcie-cfg
NAK, see writing bindings. You already received comments about generic
compatible in the past.
Best regards,
Krzysztof
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