[PATCH] dt-bindings: interrupt-controller: aspeed: Refine AST2700 binding description and example
Ryan Chen
ryan_chen at aspeedtech.com
Mon Jul 14 00:17:53 PDT 2025
- Update block diagram for better readability and accuracy.
- Clarify the relationship and function of INTC0, INTC1, and the GIC.
- Documentation and example refine.
This enhances the documentation quality and helps developers understand
the interrupt controller hierarchy and usage.
Signed-off-by: Ryan Chen <ryan_chen at aspeedtech.com>
---
.../aspeed,ast2700-intc.yaml | 155 +++++++++++++-----
1 file changed, 112 insertions(+), 43 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
index 55636d06a674..751a07d49c90 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
@@ -10,6 +10,33 @@ description:
This interrupt controller hardware is second level interrupt controller that
is hooked to a parent interrupt controller. It's useful to combine multiple
interrupt sources into 1 interrupt to parent interrupt controller.
+ Depend to which INTC0 or INTC1 used.
+ INTC0 and INTC1 are two kinds of interrupt controller with enable and raw
+ status registers for use.
+ INTC0 is used to assert GIC if interrupt in INTC1 asserted.
+ INTC1 is used to assert INTC0 if interrupt of modules asserted.
+ +-----+ +---------+
+ | GIC |---| INTC0 |
+ +-----+ +---------+
+ +---------+
+ | |---module0
+ | INTC0_0 |---module1
+ | |---...
+ +---------+---module31
+ |---.... |
+ +---------+
+ | | +---------+
+ | INTC0_11| +---| INTC1 |
+ | | +---------+
+ +---------+ +---------+---module0
+ | INTC1_0 |---module1
+ | |---...
+ +---------+---module31
+ ...
+ +---------+---module0
+ | INTC1_5 |---module1
+ | |---...
+ +---------+---module31
maintainers:
- Kevin Chen <kevin_chen at aspeedtech.com>
@@ -17,49 +44,67 @@ maintainers:
properties:
compatible:
enum:
- - aspeed,ast2700-intc-ic
+ - aspeed,ast2700-intc0
+ - aspeed,ast2700-intc1
reg:
maxItems: 1
- interrupt-controller: true
+ 'address-cells':
+ const: 2
- '#interrupt-cells':
+ 'size-cells':
const: 2
- description:
- The first cell is the IRQ number, the second cell is the trigger
- type as defined in interrupt.txt in this directory.
-
- interrupts:
- maxItems: 6
- description: |
- Depend to which INTC0 or INTC1 used.
- INTC0 and INTC1 are two kinds of interrupt controller with enable and raw
- status registers for use.
- INTC0 is used to assert GIC if interrupt in INTC1 asserted.
- INTC1 is used to assert INTC0 if interrupt of modules asserted.
- +-----+ +-------+ +---------+---module0
- | GIC |---| INTC0 |--+--| INTC1_0 |---module2
- | | | | | | |---...
- +-----+ +-------+ | +---------+---module31
- |
- | +---------+---module0
- +---| INTC1_1 |---module2
- | | |---...
- | +---------+---module31
- ...
- | +---------+---module0
- +---| INTC1_5 |---module2
- | |---...
- +---------+---module31
+ ranges: true
+
+patternProperties:
+ "^interrupt-controller@":
+ type: object
+ description: Interrupt group child nodes
+ additionalProperties: false
+
+ properties:
+ compatible:
+ enum:
+ - aspeed,ast2700-intc-ic
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+ description: |
+ The first cell is the IRQ number, the second cell is the trigger
+ type as defined in interrupt.txt in this directory.
+
+ interrupts:
+ minItems: 1
+ maxItems: 6
+ description: |
+ The interrupts provided by this interrupt controller.
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 6
+ description: |
+ This property is required when defining a cascaded interrupt controller
+ that is connected under another interrupt controller. It specifies the
+ parent interrupt(s) in the upstream controller to which this controller
+ is connected.
+
+ required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+ - interrupts
required:
- compatible
- reg
- - interrupt-controller
- - '#interrupt-cells'
- - interrupts
additionalProperties: false
@@ -68,19 +113,43 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ intc0: interrupt-controller at 12100000 {
+ compatible = "aspeed,ast2700-intc0";
+ reg = <0 0x12100000 0 0x4000>;
+ ranges = <0x0 0x0 0x0 0x12100000 0x0 0x4000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ intc0_11: interrupt-controller at 1b00 {
+ compatible = "aspeed,ast2700-intc-ic";
+ reg = <0 0x12101b00 0x10>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_SPI 193 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_SPI 194 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_SPI 195 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_SPI 196 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_SPI 197 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+
+ intc1: interrupt-controller at 14c18000 {
+ compatible = "aspeed,ast2700-intc1";
+ reg = <0 0x14c18000 0 0x400>;
+ ranges = <0x0 0x0 0x0 0x14c18000 0x0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
- interrupt-controller at 12101b00 {
- compatible = "aspeed,ast2700-intc-ic";
- reg = <0 0x12101b00 0 0x10>;
- #interrupt-cells = <2>;
- interrupt-controller;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ intc1_0: interrupt-controller at 100 {
+ compatible = "aspeed,ast2700-intc-ic";
+ reg = <0x0 0x100 0x0 0x10>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts-extended = <&intc0_11 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ };
};
--
2.34.1
More information about the linux-arm-kernel
mailing list