EDAC on imx8mp and ddr scaling

[Sherry Sun]

> -----Original Message-----
> From: Michael Nazzareno Trimarchi <michael at amarulasolutions.com>
> Sent: Friday, February 7, 2025 5:37 PM
> To: Shawn Guo <shawnguo at kernel.org>; Sherry Sun <sherry.sun at nxp.com>
> Cc: linux-arm-kernel <linux-arm-kernel at lists.infradead.org>
> Subject: EDAC on imx8mp and ddr scaling
> 
> Hi Sherry and Shawn
> 
> I have seen that with this patch "arm64: dts: imx8mp: add ddr controller node
> to support EDAC on imx8mp" but on the same time the ddr scaling is coming
> from arm_smccc_smc DVFS frequency scaling that is managed from imx8m-
> ddrc. We have tested it a bit to understand if the circle to have the code call
> from linux to ATF was somehow working. We don't check other than small
> things.
> If the imx8mp is compatible with imx8m-ddrc and synopsys memory
> controller, should not needed to merge the support in the synopsys
> connected to the board platform data?
> 

Hi Michael,

The imx8m-ddrc you reference here is totally different thing with the
synopsys_edac that my patch adds.
imx8m-ddrc targets dynamic frequency scaling of DRAM, while synopsys_edac
targets DDR ECC feature(error detection and correction).

Best Regards
Sherry

> Best regards
> Michael