[PATCH v2 1/2] arm64: dts: s32g: Add S32G2/S32G3 uSDHC pinmux

[Krzysztof Kozlowski]

On 30/08/2024 13:33, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea at oss.nxp.com>
> 
> Adding 100mhz & 200mhz pinmux support for uSDHC helps to enable
> higher speed modes for SD (SDR50, DDR50, SDR104) and
> eMMC (such as HS200, HS400/HS400ES).
> 
> Signed-off-by: Radu Pirea <radu-nicolae.pirea at nxp.com>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea at oss.nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/s32g2.dtsi      | 153 ++++++++++++++++++
>  .../arm64/boot/dts/freescale/s32g274a-evb.dts |   4 +
>  .../boot/dts/freescale/s32g274a-rdb2.dts      |   4 +
>  arch/arm64/boot/dts/freescale/s32g3.dtsi      | 153 ++++++++++++++++++
>  .../boot/dts/freescale/s32g399a-rdb3.dts      |   4 +
>  5 files changed, 318 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index fa054bfe7d5c..7be430b78c83 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -162,6 +162,159 @@ jtag-grp4 {
>  					slew-rate = <166>;
>  				};
>  			};
> +
> +			pinctrl_usdhc0: usdhc0grp-pins {
> +				usdhc0-grp0 {

Are you sure that this passes dtbs_check W=1?

Best regards,
Krzysztof