[PATCH 1/2] dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5 controller-1.
Havalige, Thippeswamy
thippeswamy.havalige at amd.com
Fri Sep 6 03:50:48 PDT 2024
Hi Krzysztof,
> -----Original Message-----
> From: Krzysztof Kozlowski <krzk at kernel.org>
> Sent: Friday, September 6, 2024 4:16 PM
> To: Havalige, Thippeswamy <thippeswamy.havalige at amd.com>;
> manivannan.sadhasivam at linaro.org; robh at kernel.org; linux-
> pci at vger.kernel.org; bhelgaas at google.com; linux-arm-
> kernel at lists.infradead.org; linux-kernel at vger.kernel.org;
> krzk+dt at kernel.org; conor+dt at kernel.org; devicetree at vger.kernel.org
> Cc: Gogada, Bharat Kumar <bharat.kumar.gogada at amd.com>; Simek,
> Michal <michal.simek at amd.com>; lpieralisi at kernel.org; kw at linux.com
> Subject: Re: [PATCH 1/2] dt-bindings: PCI: xilinx-cpm: Add compatible string
> for CPM5 controller-1.
>
> On 06/09/2024 12:43, Havalige, Thippeswamy wrote:
> > Hi Krzysztof
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk at kernel.org>
> >> Sent: Friday, September 6, 2024 3:26 PM
> >> To: Havalige, Thippeswamy <thippeswamy.havalige at amd.com>;
> >> manivannan.sadhasivam at linaro.org; robh at kernel.org; linux-
> >> pci at vger.kernel.org; bhelgaas at google.com; linux-arm-
> >> kernel at lists.infradead.org; linux-kernel at vger.kernel.org;
> >> krzk+dt at kernel.org; conor+dt at kernel.org; devicetree at vger.kernel.org
> >> Cc: Gogada, Bharat Kumar <bharat.kumar.gogada at amd.com>; Simek,
> Michal
> >> <michal.simek at amd.com>; lpieralisi at kernel.org; kw at linux.com
> >> Subject: Re: [PATCH 1/2] dt-bindings: PCI: xilinx-cpm: Add compatible
> >> string for CPM5 controller-1.
> >>
> >> On 06/09/2024 11:31, Thippeswamy Havalige wrote:
> >>> The Xilinx Versal premium series has CPM5 block which supports two
> >>> typeA Root Port controller functionality at Gen5 speed.
> >>>
> >>> Add compatible string to distinguish between two CPM5 rootport
> >> controller1.
> >>
> >> Subjects NEVER end with full stops.
> > Thanks, Update in the next patch series.
> >>>
> >>> Error interrupt register and bits for both the controllers are at
> >>> different.
> >>>
> >>> Signed-off-by: Thippeswamy Havalige <thippesw at amd.com>
> >>> ---
> >>> Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 1 +
> >>> 1 file changed, 1 insertion(+)
> >>>
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> >>> b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> >>> index 989fb0fa2577..b63a759ec2d7 100644
> >>> --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> >>> +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> >>> @@ -17,6 +17,7 @@ properties:
> >>> enum:
> >>> - xlnx,versal-cpm-host-1.00
> >>> - xlnx,versal-cpm5-host
> >>> + - xlnx,versal-cpm5-host1
> >>
> >> That's poor naming. "-1.00" and now "1". Get your naming reasonable...
> > Here 1.00 represents the IP versioning and host1 represents controller-1.
>
> I understand but you repeating the same is not helping. Make it better and
> next time upstream "host1-1" compatible.
>
> Number of ports, BTW, comes from ports, right? So no need for the
> compatible.
To differentiate between the registers for Controller-0 and Controller-1, I am utilizing a compatible string in the driver. This approach enables the driver to identify and manage the registers associated with each controller based on the specified compatible string.
> Best regards,
> Krzysztof
Regards,
Thippeswamy H
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