[PATCH 02/11] clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs
Taniya Das
quic_tdas at quicinc.com
Wed Oct 30 10:52:08 PDT 2024
On 10/19/2024 1:50 AM, Christophe JAILLET wrote:
>> +
>> +static int clk_alpha_pll_slew_update(struct clk_alpha_pll *pll)
>> +{
>> + int ret = 0;
>
> Nitpick: unneeded initialisation
>
Will fix in the next patch.
>> + u32 val;
>> +
>> + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
>> PLL_UPDATE);
>> + regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
>> +
>> + ret = wait_for_pll_update(pll);
>> + if (ret)
>> + return ret;
>> + /*
>> + * Hardware programming mandates a wait of at least 570ns before
>> polling the LOCK
>> + * detect bit. Have a delay of 1us just to be safe.
>> + */
>> + mb();
>> + udelay(1);
>> +
>> + return wait_for_pll_enable_lock(pll);
>> +}
>
> ...
>
>> +static int clk_alpha_pll_slew_enable(struct clk_hw *hw)
>> +{
>> + int rc;
>> +
>> + rc = clk_alpha_pll_calibrate(hw);
>> + if (rc)
>> + return rc;
>> +
>> + rc = clk_alpha_pll_enable(hw);
>> +
>> + return rc;
>
> Nitpick: return clk_alpha_pll_enable(hw);
Will fix in the next patch.
--
Thanks & Regards,
Taniya Das.
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