[PATCH 02/11] clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs

[Christophe JAILLET]

Le 18/10/2024 à 21:15, Taniya Das a écrit :
> The alpha PLLs which slew to a new frequency at runtime would require
> the PLL to calibrate at the mid point of the VCO. Add the new PLL ops
> which can support the slewing of the PLL to a new frequency.
> 
> Signed-off-by: Taniya Das <quic_tdas at quicinc.com>
> ---
>   drivers/clk/qcom/clk-alpha-pll.c | 172 +++++++++++++++++++++++++++++++++++++++
>   drivers/clk/qcom/clk-alpha-pll.h |   1 +
>   2 files changed, 173 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 03cc7aa092480bfdd9eaa986d44f0545944b3b89..6f51bdd2b500ceeccbca0aefd5003df10ad1e1ae 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -2758,3 +2758,175 @@ const struct clk_ops clk_alpha_pll_regera_ops = {
>   	.set_rate = clk_zonda_pll_set_rate,
>   };
>   EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);
> +
> +static int clk_alpha_pll_slew_update(struct clk_alpha_pll *pll)
> +{
> +	int ret = 0;

Nitpick: unneeded initialisation

> +	u32 val;
> +
> +	regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, PLL_UPDATE);
> +	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
> +
> +	ret = wait_for_pll_update(pll);
> +	if (ret)
> +		return ret;
> +	/*
> +	 * Hardware programming mandates a wait of at least 570ns before polling the LOCK
> +	 * detect bit. Have a delay of 1us just to be safe.
> +	 */
> +	mb();
> +	udelay(1);
> +
> +	return wait_for_pll_enable_lock(pll);
> +}

...

> +static int clk_alpha_pll_slew_enable(struct clk_hw *hw)
> +{
> +	int rc;
> +
> +	rc = clk_alpha_pll_calibrate(hw);
> +	if (rc)
> +		return rc;
> +
> +	rc = clk_alpha_pll_enable(hw);
> +
> +	return rc;

Nitpick: return clk_alpha_pll_enable(hw);

> +}
> +