[PATCH] clk: imx: pll14xx: Extend dynamic rates support to PLL1416x

[Marek Vasut]

On 11/12/24 4:26 AM, Liu Ying wrote:
> On 11/12/2024, Marek Vasut wrote:
>> The pll1416x PLL so far only supports rates from a rate table passed
>> during initialization. Calculating PLL settings dynamically helps in
>> case e.g. multiple video outputs are used and they each need their own
>> separate source of accurate pixel clock on i.MX8MP. In that case, e.g.
>> PLL1416x PLL3 can be used as another Video PLL for another output.
> 
> Just want to point out that i.MX8MP audio AXI clock is supposed to be
> derived from PLL3 to run at 600MHz in nominal mode(i.MX8MP data sheet
> specifies that rate).  So, if a particular i.MX8MP system doesn't use
> audio, PLL3 can be a free clock source to be used by an i.MX8MP display
> pipeline, otherwise, video_pll1_out is supposed to be shared by i.MX8MP
> MIPI DSI and LVDS display pipelines.

In the end, I started using Audio PLL and Video PLL PLL1443x for 
accurate pixel clock generation and PLL3 to feed CLKOUTn where the less 
accurate PLL3 PLL1416x is just fine.

With the disparate display requirements, sharing one Video PLL for 
multiple outputs like DSI and LVDS is unrealistic. (maybe the next SoC 
should have some nice PLL per display output)

> Currently, IMX8MP_CLK_AUDIO_AXI_SRC's parent is assigned to
> IMX8MP_SYS_PLL1_800M in imx8mp.dtsi.  Although it's rate is assigned
> to 600MHz, the actual rate is 400MHz according to clk_summary because
> the divider cannot find a ratio to reach 600MHz from the clock source
> running at 800MHz.  Looking at imx8mp_audio_axi_sels[], sys_pll3_out
> is the only free/appropriate clock source that can derive 600MHz audio
> AXI clock from.  Maybe, someone will change IMX8MP_CLK_AUDIO_AXI_SRC's
> parent to IMX8MP_SYS_PLL3_OUT ?
Is the 400 MHz sufficient for audio-axi or does it have some negative 
performance impact ? If the later, better send a patch to use PLL3 for 
audio-axi .

Thanks !