[PATCH] clk: imx: pll14xx: Extend dynamic rates support to PLL1416x

[Liu Ying]

On 11/12/2024, Marek Vasut wrote:
> The pll1416x PLL so far only supports rates from a rate table passed
> during initialization. Calculating PLL settings dynamically helps in
> case e.g. multiple video outputs are used and they each need their own
> separate source of accurate pixel clock on i.MX8MP. In that case, e.g.
> PLL1416x PLL3 can be used as another Video PLL for another output.

Just want to point out that i.MX8MP audio AXI clock is supposed to be
derived from PLL3 to run at 600MHz in nominal mode(i.MX8MP data sheet
specifies that rate).  So, if a particular i.MX8MP system doesn't use
audio, PLL3 can be a free clock source to be used by an i.MX8MP display
pipeline, otherwise, video_pll1_out is supposed to be shared by i.MX8MP
MIPI DSI and LVDS display pipelines.

Currently, IMX8MP_CLK_AUDIO_AXI_SRC's parent is assigned to
IMX8MP_SYS_PLL1_800M in imx8mp.dtsi.  Although it's rate is assigned
to 600MHz, the actual rate is 400MHz according to clk_summary because
the divider cannot find a ratio to reach 600MHz from the clock source
running at 800MHz.  Looking at imx8mp_audio_axi_sels[], sys_pll3_out
is the only free/appropriate clock source that can derive 600MHz audio
AXI clock from.  Maybe, someone will change IMX8MP_CLK_AUDIO_AXI_SRC's
parent to IMX8MP_SYS_PLL3_OUT ?

pgc_audio: power-domain at 5 {                                                      
        #power-domain-cells = <0>;                                               
        reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;                                    
        clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,                                   
                 <&clk IMX8MP_CLK_AUDIO_AXI>;                                    
        assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,                           
                          <&clk IMX8MP_CLK_AUDIO_AXI_SRC>;                       
        assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,                    
                                 <&clk IMX8MP_SYS_PLL1_800M>;                    
        assigned-clock-rates = <400000000>,                                      
                               <600000000>;                                      
};

      sys_pll1_ref_sel                 1       1        0        24000000    0          0     50000      Y      deviceless                      no_connection_id         
       sys_pll1                      1       1        0        800000000   0          0     50000      Y         deviceless                      no_connection_id         
          sys_pll1_bypass            1       1        0        800000000   0          0     50000      Y            deviceless                      no_connection_id         
             sys_pll1_out            4       4        0        800000000   0          0     50000      Y               deviceless                      no_connection_id         
                sys_pll1_800m        6       6        0        800000000   0          0     50000      Y                  deviceless                      no_connection_id          

                ...

                   audio_axi         1       1        0        400000000   0          0     50000      Y                     power-domain at 5                  no_connection_id         
                                                                                                                             deviceless                      no_connection_id         
                      audio_axi_root 0       0        0        400000000   0          0     50000      Y                        deviceless                      no_connection_id     

-- 
Regards,
Liu Ying