[PATCH v2 2/2] arm64: dts: imx93-phycore-segin: Add Phytec i.MX93 Segin

Primoz Fiser primoz.fiser at norik.com
Thu Jan 18 01:58:36 PST 2024 

Hi Mathieu,

first of all, nice to see an attempt to upstream the board. A bit fast
though as upstreaming was planned after the official PHYTEC release.

However, there is quite a lot of differences in respect to the
downstream PHYTEC kernel tree.

I am sure PHYTEC wants to sync here to avoid general confusion.

CC-ing: upstream at list.phytec.de

So lets start:

- the board should be named "imx93-phyboard-segin" instead of
"imx93-phycore-segin".

PHYTEC naming convention:
phyCORE -> the SoM
phyBOARD -> the base board (with the SoM)


On 17. 01. 24 08:49, Mathieu Othacehe wrote:
> Add DTSI for Phytec i.MX93 System on Module and DTS for Phytec
> i.MX93 on Segin evaluation board.
> 
> This version comes with:
>  - 1GB LPDDR4 RAM
>  - external SD
>  - debug UART
>  - 1x 100Mbit Ethernet

Maybe you sync this commit msg + title with downstream commit like so:

>     arm64: dts: imx93: Add phyBOARD-Segin-i.MX93 support
>     
>     Add basic support for phyBOARD-Segin-i.MX93.
>     Main features are:
>     * Ethernet
>     * SD-Card
>     * UART
>     

plus add eMMC to the list if you decided to enable it?


> 
> Signed-off-by: Mathieu Othacehe <othacehe at gnu.org>
> ---
>  arch/arm64/boot/dts/freescale/Makefile        |  1 +
>  .../dts/freescale/imx93-phycore-segin.dts     | 93 +++++++++++++++++++
>  .../boot/dts/freescale/imx93-phycore-som.dtsi | 64 +++++++++++++
>  3 files changed, 158 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx93-phycore-segin.dts
>  create mode 100644 arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> 
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 2e027675d7bb..f078d6ef75f7 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -201,6 +201,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-segin.dtb

Like I said, this has to be renamed to imx93-phyboard-segin.dts as the
official kit name is "phyBOARD-Segin-i.MX93".

>  dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
>  
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phycore-segin.dts
> new file mode 100644
> index 000000000000..748b779a9dc1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-segin.dts> @@ -0,0 +1,93 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2023 PHYTEC Messtechnik GmbH
> + * Christoph Stoidner <c.stoidner at phytec.de>
> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe at gmail.com>
> + *
> + */
> +/dts-v1/;
> +
> +#include "imx93-phycore-som.dtsi"
> +
> +/{
> +	model = "PHYTEC phyBOARD-Segin-i.MX93";
> +	compatible = "phytec,imx93-phycore-segin", "phytec,imx93-phycore-som",
> +		     "fsl,imx93";
> +
> +	chosen {
> +		stdout-path = &lpuart1;
> +	};
> +
> +	reg_usdhc2_vmmc: regulator-usdhc2 {
> +		compatible = "regulator-fixed";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
> +		regulator-name = "VSD_3V3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;

Order properties here alphabetically like in the downstream kernel.

Comment applies for the entire patch.

> +	};
> +};
> +
> +/* Console */
> +&lpuart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1>;
> +	status = "okay";
> +};
> +
> +/* SD-Card */
> +&usdhc2 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
> +	vmmc-supply = <&reg_usdhc2_vmmc>;
> +	bus-width = <4>;
> +	status = "okay";
> +	no-sdio;
> +	no-mmc;
> +};
> +

Please consider adding pinctrl_100mhz and pinctrl_200mhz from the
downstream kernel which were determined by HW measurements at those
operating frequencies.


> +/* Watchdog */
> +&wdog3 {
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	status = "okay";

Remove this pinctrl + status left-over?

> +
> +	pinctrl_uart1: uart1grp {
> +		fsl,pins = <
> +			MX93_PAD_UART1_RXD__LPUART1_RX			0x31e
> +			MX93_PAD_UART1_TXD__LPUART1_TX			0x31e

Please consider pinctrl settings from the down-stream kernel. They differ.

> +		>;
> +	};
> +
> +	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
> +		fsl,pins = <
> +			MX93_PAD_SD2_RESET_B__GPIO3_IO07		0x31e
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> +		fsl,pins = <
> +			MX93_PAD_SD2_CD_B__GPIO3_IO00			0x31e
> +		>;
> +	};
> +
> +	pinctrl_usdhc2: usdhc2grp {
> +		fsl,pins = <
> +			MX93_PAD_SD2_CLK__USDHC2_CLK			0x178e
> +			MX93_PAD_SD2_CMD__USDHC2_CMD			0x139e
> +			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x138e
> +			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x138e
> +			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x138e
> +			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x139e
> +			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e
> +		>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> new file mode 100644
> index 000000000000..4edff4a50b2b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
> @@ -0,0 +1,64 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2023 PHYTEC Messtechnik GmbH
> + * Christoph Stoidner <c.stoidner at phytec.de>
> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe at gmail.com>
> + *
> + */
> +/dts-v1/;
> +
> +#include "imx93.dtsi"
> +
> +/{
> +	model = "PHYTEC phyCORE-i.MX93";
> +	compatible = "phytec,imx93-phycore-som", "fsl,imx93";
> +
> +	reserved-memory {
> +		ranges;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +
> +		linux,cma {
> +			compatible = "shared-dma-pool";
> +			reusable;
> +			alloc-ranges = <0 0x80000000 0 0x40000000>;
> +			size = <0 0x10000000>;
> +			linux,cma-default;
> +		};
> +
> +		ele_reserved: ele-reserved at a4120000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0 0xa4120000 0 0x100000>;
> +			no-map;
> +		};

Remove ele_reserved if you are not using it anywhere. This only applies
to vendor kernel at the moment.

> +	};
> +};
> +
> +/* eMMC */
> +&usdhc1 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc1>;
> +	pinctrl-1 = <&pinctrl_usdhc1>;
> +	pinctrl-2 = <&pinctrl_usdhc1>;
> +	bus-width = <8>;
> +	non-removable;
> +	status = "okay";

Currently only default DDR50 is supported.

So no need for 100mhz + 200mhz pinctrls.

> +};
> +
> +&iomuxc {
> +	pinctrl_usdhc1: usdhc1grp {
> +		fsl,pins = <
> +			MX93_PAD_SD1_CLK__USDHC1_CLK		0x15fe
> +			MX93_PAD_SD1_CMD__USDHC1_CMD		0x13fe
> +			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe
> +			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe
> +			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe
> +			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe
> +			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe
> +			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe
> +			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe
> +			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe
> +			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe
> +		>;
> +	};
> +};

BR,
Primoz

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