[PATCH 1/6] net: driver: stmmac: extend CSR calc support

[Serge Semin]

Hi Andrew

On Mon, Aug 05, 2024 at 01:11:16AM +0200, Andrew Lunn wrote:
> >  #define	STMMAC_CSR_20_35M	0x2	/* MDC = clk_scr_i/16 */
> >  #define	STMMAC_CSR_35_60M	0x3	/* MDC = clk_scr_i/26 */
> >  #define	STMMAC_CSR_150_250M	0x4	/* MDC = clk_scr_i/102 */
> > -#define	STMMAC_CSR_250_300M	0x5	/* MDC = clk_scr_i/122 */
> > +#define	STMMAC_CSR_250_300M	0x5	/* MDC = clk_scr_i/124 */
> 
> That should probably be called out in the commit message. It is not a
> fix as such, since it is just a comment, but as a reviewer i had a
> double take when i noticed this.,

Yes, this seems like a typo. I've checked the divider semantic in the DW
GMAC 3.50a/3.73a and DW QoS Eth 5.10a HW databooks. Both of them expect the
clk_scr_i ref clock being divided by 124. So the 122 value was
incorrect.

-Serge(y)

> 
> 
>     Andrew
> 
> ---
> pw-bot: cr
>