[PATCH v2 2/3] ARM: dts: renesas: r8a7740: Add LCDC nodes

[Geert Uytterhoeven]

Add device nodes for the two LCD Controllers (LCDC) on the R-Mobile A1
SoC, and for the two optional external LCDL clock inputs.

Note that the HDMI clock for LCDC1 is not added, as this clock is not
yet supported.

Based on a patch by Laurent Pinchart adding the first LCDC device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas at glider.be>
---
v2:
  - No changes.

Changes compared to Laurent's original:
  - Add lcdc0 label,
  - Rename node from display to lcdc-controller,
  - Rename compatible value from "renesas,lcdc-r8a7740" to
    "renesas,r8a7740-lcdc",
  - Correct syntax of reg property,
  - Use GIC_SPI macro,
  - Add more clocks,
  - Add power-domains property,
  - Add status disabled,
  - Remove second port from lcdc0, as only lcdc1 has an HDMI port,
  - Add lcdc1 device node.
---
 arch/arm/boot/dts/renesas/r8a7740.dtsi | 65 ++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi
index 1b2cf5fa322b2985..55884ec701f8dab4 100644
--- a/arch/arm/boot/dts/renesas/r8a7740.dtsi
+++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi
@@ -398,6 +398,61 @@ sh_fsi2: sound at fe1f0000 {
 		status = "disabled";
 	};
 
+	lcdc0: lcd-controller at fe940000 {
+		compatible = "renesas,r8a7740-lcdc";
+		reg = <0xfe940000 0x4000>;
+		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp1_clks R8A7740_CLK_LCDC0>,
+			 <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk0_clk>,
+			 <&vou_clk>;
+		clock-names = "fck", "media", "lclk", "video";
+		power-domains = <&pd_a4lc>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port at 0 {
+				reg = <0>;
+
+				lcdc0_rgb: endpoint {
+				};
+			};
+		};
+	};
+
+	lcdc1: lcd-controller at fe944000 {
+		compatible = "renesas,r8a7740-lcdc";
+		reg = <0xfe944000 0x4000>;
+		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp1_clks R8A7740_CLK_LCDC1>,
+			 <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk1_clk>,
+			 <&vou_clk>;
+		clock-names = "fck", "media", "lclk", "video";
+		power-domains = <&pd_a4lc>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port at 0 {
+				reg = <0>;
+
+				lcdc1_rgb: endpoint {
+				};
+			};
+
+			port at 1 {
+				reg = <1>;
+
+				lcdc1_hdmi: endpoint {
+				};
+			};
+		};
+	};
+
 	tmu0: timer at fff80000 {
 		compatible = "renesas,tmu-r8a7740", "renesas,tmu";
 		reg = <0xfff80000 0x2c>;
@@ -474,6 +529,16 @@ fsibck_clk: fsibck {
 			#clock-cells = <0>;
 			clock-frequency = <0>;
 		};
+		lcdlclk0_clk: lcdlclk0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+		lcdlclk1_clk: lcdlclk1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
 
 		/* Special CPG clocks */
 		cpg_clocks: cpg_clocks at e6150000 {
-- 
2.34.1