[PATCH 07/23] arm64: zynqmp: Add pmu interrupt-affinity

[Michal Simek]

On 5/16/23 13:05, Michal Simek wrote:
> 
> 
> On 5/2/23 15:35, Michal Simek wrote:
>> From: Radhey Shyam Pandey <radhey.shyam.pandey at amd.com>
>>
>> Explicitly specify interrupt affinity to avoid HW perfevents
>> need to guess. This avoids the following error upon linux boot:
>> armv8-pmu pmu: hw perfevents: no interrupt-affinity property,
>> guessing.
>>
>> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey at amd.com>
>> Signed-off-by: Michal Simek <michal.simek at amd.com>
>> ---
>>
>>   arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi 
>> b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>> index 61c7045eb992..a117294dc890 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>> @@ -161,6 +161,10 @@ pmu {
>>                    <0 144 4>,
>>                    <0 145 4>,
>>                    <0 146 4>;
>> +        interrupt-affinity = <&cpu0>,
>> +                     <&cpu1>,
>> +                     <&cpu2>,
>> +                     <&cpu3>;
>>       };
>>       psci {
> 
> Applied.
> M

Actually remove this one from my queue because there were comment from Laurent.

M



-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs