[PATCH 2/2] KVM: arm64: Move FGT value configuration to vCPU state

[Marc Zyngier]

On Fri, 17 Mar 2023 13:49:44 +0000,
Mark Brown <broonie at kernel.org> wrote:
> 
> On Fri, Mar 17, 2023 at 09:02:32AM +0000, Marc Zyngier wrote:
> > Mark Brown <broonie at kernel.org> wrote:
> 
> > > +	vcpu->arch.hfgrtr_el2 = 0;
> > > +	vcpu->arch.hfgwtr_el2 = 0;
> 
> > Although this looks completely innocent, this actually have the effect
> > of trapping the SMPRI_EL1 and TPIDR2_EL0 registers, something that is
> > self documented in the current code, and that completely disappears
> > with this patch.
> 
> > This needs documenting by enumerating the sysregs that get trapped.
> 
> That's an awful lot of registers with the fine grained traps, and when
> extended to cover HFHxTR2 there's a bunch of RES0 bits intended for
> future traps.  It feels a bit unmanagable.  I'd have expected something
> more along the lines of "enable all traps other than...".  The pattern
> seemed to be more to have an explicit initialiser for the bits that are
> set (eg, with CPACR_EL1) which was why I didn't put anything explicit. 

"an awful lot of registers" is exactly 3 registers as of ARMv8.8/9.3
that have a disable-trapping-when-set pattern. Maybe more in 9.4 and
up, but if people can be bothered to write the tools/sysreg file, they
can also document what gets implicitly trapped.

This also outlines that ACCDATA_EL1 gets trapped while it wasn't
explicitly trapped before, and that we don't have a handler for it.

So we need an extensive documentation of what the 0 value covers, no
ifs no buts.

	M.

-- 
Without deviation from the norm, progress is not possible.