Conflict between video-lut and pmu on meson-g12

[Martin Blumenstingl]

Hi Marc,

On Thu, Mar 9, 2023 at 10:48 AM Marc Gonzalez <marc.w.gonzalez at free.fr> wrote:
[...]
> Any ideas/suggestions?
> How do we proceed?
I suggest you go ahead and send your original diff as formal patches.
It would be best to have two/three patches (that can go through
different maintainers repositories if needed):
- move &pmu into &dmc, update the register size (as you suggested) and
also update the offset (since they will have to be calculated based on
&dmc)
- fix up the #defines in the driver as you suggested
- nice to have: update the example in
Documentation/devicetree/bindings/perf/amlogic,g12-ddr-pmu.yaml

Before we work on the XTAL clock input I think it's best if we know
about the actual hardware setup.
amlogic,g12-ddr-pmu.yaml mentions that the second register set is for
the "DMC PLL register space".
I suspect that the DMC PLL has two purposes:
- it's used as timer/counter for the PMU
- it is also used for clocking the DDR memory

If this assumption is correct then I think that the DMC PLL should get
a separate node (with XTAL as clock input). Then the DMC PLL output
should be used as clock input for the &pmu node.
The reason for this is that the device tree should describe the
hardware, not drivers. Also device tree is not Linux specific, it can
be used by u-boot, etc.
So if someone would implement the DDR setup in u-boot (or another
bootloader - which may even share the device tree with Linux) then it
has to be described correctly.
I'm hoping that Jiucheng can provide his input on this topic.

By the way: we already have a DDR (PLL) driver in
drivers/clk/meson/meson8-ddr.c. At this point in time it only has
Meson8/Meson8b/Meson8m2 support. I suspect it will be easy to extend
the existing driver or just write a new one.


Best regards,
Martin