Conflict between video-lut and pmu on meson-g12

[Marc Gonzalez]

On 01/03/2023 14:28, Marc Gonzalez wrote:

> On 28/02/2023 22:49, Martin Blumenstingl wrote:
> 
>> While thinking more about this - I think the whole .dtsi code should
>> be improved. Both of the PMU IO regions are part of the &dmc region.
>> So I think &pmu should be moved inside &dmc (with the offsets adjusted
>> accordingly of course).
>>
>> Also I think the dt-bindings are incomplete: according to the driver
>> code we're using XTAL as input clock.
>> But this is not described anywhere in the dt-bindings.
>> dt-bindings should always describe the hardware. The driver can decide
>> not to use it but the bindings must always be complete.
>> And with this comes the question: is the DMC PLL specific to the PMU
>> or is it shared with something else (e.g. the actual memory
>> controller)? On the 32-bit SoCs (Meson8b/S805 for example) there's a
>> whole DDR clock controller (used by the DDR memory controller), so I'm
>> wondering if these newer SoCs are still following that approach.
> 
> FWIW, the vendor device-tree specifies the following nodes:
> https://android.googlesource.com/kernel/arm64/+/f5269100977385d1fd4a5ef68e49631892cf4fe4/arch/arm64/boot/dts/amlogic/g12a_s905x2_u215.dts
> 
> 	canvas {
> 		compatible = "amlogic, meson, canvas";
> 		dev_name = "amlogic-canvas";
> 		status = "okay";
> 		reg = <0x0 0xff638000 0x0 0x2000>;
> 		phandle = <0x111>;
> 	};
> 
> 	codec_io {
> 		compatible = "amlogic, codec_io";
> 		status = "okay";
> 		#address-cells = <0x2>;
> 		#size-cells = <0x2>;
> 		ranges;
> 		phandle = <0x112>;
> 		[...]
> 		io_dmc_base {
> 			reg = <0x0 0xff638000 0x0 0x2000>;
> 		};
> 	};
> 
> 	ddr_bandwidth {
> 		compatible = "amlogic, ddr-bandwidth";
> 		status = "okay";
> 		reg = <0x0 0xff638000 0x0 0x100 0x0 0xff638c00 0x0 0x100>;
> 		sec_base = <0xff639000>;
> 		interrupts = <0x0 0x34 0x1>;
> 		interrupt-names = "ddr_bandwidth";
> 	};
> 
> 
> I don't understand how it's possible to have 3 overlapping ranges?
> Unless the respective drivers know to map only specific ranges?
> 
> 
> Regarding your DMC (DDR memory controller) clock question,
> clock tree seems to be:
> 24 MHz XTAL feeds DDR_PLL block,
> which outputs DDR_CLK pulse for the DMC.
> 
> 
> Something I do not understand is that the datasheet states:
> DMC unsecure register. Base address 0xFF638000.
> Offset 0 = AM_DDR_PLL_CNTL0
> Offset 4 = AM_DDR_PLL_CNTL1
> ...
> 
> And then also states:
> The following registers' base address is 0xff638000.
> Offset 0 = DMC_REQ_CTRL
> Offset 4 = DMC_SOFT_RST
> ...
> 
> And these two register sets have nothing in common
> (except the SAME base address...)
> 
> https://android.googlesource.com/kernel/arm64/+/f5269100977385d1fd4a5ef68e49631892cf4fe4/include/linux/amlogic/media/registers/regs/dmc_regs.h
> 
> Is there perhaps a typo in one of the base addresses?


Any ideas/suggestions?
How do we proceed?

Regards