NXP imx6ull nonalignment buffer question

[Bough Chen]

> -----Original Message-----
> From: Michael Nazzareno Trimarchi <michael at amarulasolutions.com>
> Sent: 2023年2月27日 19:22
> To: Bough Chen <haibo.chen at nxp.com>
> Cc: Shawn Guo <shawnguo at kernel.org>; Fabio Estevam
> <festevam at gmail.com>; LKML <linux-kernel at vger.kernel.org>;
> linux-arm-kernel <linux-arm-kernel at lists.infradead.org>;
> linux-mmc at vger.kernel.org; Ulf Hansson <ulf.hansson at linaro.org>
> Subject: Re: NXP imx6ull nonalignment buffer question
> 
> Hi Bough
> 
> On Fri, Jan 13, 2023 at 8:19 AM Michael Nazzareno Trimarchi
> <michael at amarulasolutions.com> wrote:
> >
> > Hi
> >
> > On Fri, Jan 13, 2023 at 4:30 AM Bough Chen <haibo.chen at nxp.com> wrote:
> > >
> > > > -----Original Message-----
> > > > From: Michael Nazzareno Trimarchi <michael at amarulasolutions.com>
> > > > Sent: 2023年1月9日 21:02
> > > > To: Bough Chen <haibo.chen at nxp.com>; Shawn Guo
> > > > <shawnguo at kernel.org>; Fabio Estevam <festevam at gmail.com>; LKML
> > > > <linux-kernel at vger.kernel.org>
> > > > Cc: linux-arm-kernel <linux-arm-kernel at lists.infradead.org>;
> > > > linux-mmc at vger.kernel.org; Ulf Hansson <ulf.hansson at linaro.org>
> > > > Subject: NXP imx6ull nonalignment buffer question
> > > >
> > > > Hi Haibo
> > > >
> > > > Working on imx6ulz design and found that if I send a sdio packet
> > > > using the sdio_writesb the adma driver tries to handle it with two
> > > > dma descriptors. The first one filled with the bytes up to 3 to
> > > > cover the misalign and then another buffer descriptor
> > > >
> > > >   offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
> > > >                          SDHCI_ADMA2_MASK;
> > > >                 if (offset) {
> > > >                         if (data->flags & MMC_DATA_WRITE) {
> > > >                                 buffer = sdhci_kmap_atomic(sg);
> > > >                                 memcpy(align, buffer, offset);
> > > >                                 sdhci_kunmap_atomic(buffer);
> > > >                         }
> > > >
> > > >                         /* tran, valid */
> > > >                         __sdhci_adma_write_desc(host, &desc,
> > > > align_addr,
> > > >                                                 offset,
> > > > ADMA2_TRAN_VALID);
> > > >
> > > >                         BUG_ON(offset > 65536);
> > > >
> > > >                         align += SDHCI_ADMA2_ALIGN;
> > > >                         align_addr += SDHCI_ADMA2_ALIGN;
> > > >
> > > >                         addr += offset;
> > > >                         len -= offset;
> > > >                 }
> > > >
> > > > In 48.7.4 Data Length Setting
> > > > For either ADMA (ADMA1 or ADMA2) transfer, the data in the data
> > > > buffer must be word aligned, so the data length set in the descriptor must
> be a multiple of 4.
> > > > I have noticed that this code does not work as expected.
> > >
> > > Hi Michael,
> > >
> > > My understanding is: for the sentence " the data in the data buffer must be
> word aligned", this means the start address of the data must be word aligned,
> but not limit the data length.
> > >
> >
> > Ok. My specific problem is that this seems not working on imx6ulz, I
> > found the problem working on a wifi chipset, if the request gets split
> > for no-alignment of the data in two dma descriptors, the chipset does
> > not reply to me.
> > Anyway, I will retest it with the upstream kernel again. I will check
> > better and I will follow up if any more question
> >
> 
> I have done some tests and I need this quirk SDHCI_QUIRK_32BIT_ADMA_SIZE
> on imx6ulz cpu and I think that it applies even on imx6ull.
> Wifi can work only if the data on the sdio are aligned or we use interrupt mode
> for no-alignment data. I did not find an errata and I can not add as a quirk
> without a confirmation
> 

Hi Michael,

If use the quirk SDHCI_QUIRK_32BIT_ADMA_SIZE, for the length no-alignment data, it will
change to use PIO mode.

Here, can you give some more details about this issue? When the dma descriptor contain the
no-alignment length of data, is there any register dump on the console? Or meet any timeout? Or there any
ADMA length mismatch happen? 

Besides, did you try DMA mode instead of the ADMA mode? Can DMA mode work for your case?

Best Regards
Haibo Chen

> Michael