SR-IOV on ARM64 system with SMMU

[Martin Bayern]

hi Robin,


I find this this pcie node in their hardware include, its status is 
disabled, there is iommus = <&smmu TEGRA_SID_PCIE5>;   and the pcie_ep 
is 0x141a0000, is this what you are refer to?


         pcie_ep at 141a0000 {
                 compatible = "nvidia,tegra194-pcie-ep";
                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;

                 reg = <0x00 0x141a0000 0x0 0x00020000   /* appl 
registers (128K)      */
                        0x00 0x3a000000 0x0 0x00040000   /* 
configuration space (256K) */
                        0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg 
space (256K)  */
                        0x00 0x3a080000 0x0 0x00040000   /* DBI reg 
space (256K)       */
                        0x1c 0x00000000 0x4 0x00000000>; /* Address 
Space (16G)        */
                 reg-names = "appl", "config", "atu_dma", "dbi", 
"addr_space";

                 #address-cells = <3>;
                 #size-cells = <2>;

                 status = "disabled";

                 clocks = <&bpmp_clks TEGRA194_CLK_PEX1_CORE_5>;
                 clock-names = "core";

                 resets = <&bpmp_resets TEGRA194_RESET_PEX1_CORE_5_APB>,
                          <&bpmp_resets TEGRA194_RESET_PEX1_CORE_5>;
                 reset-names = "apb", "core";

                 interrupts = <0 53 0x04>;       /* controller interrupt */
                 interrupt-names = "intr";

                 pinctrl-names = "default";
                 pinctrl-0 = <&pex_rst_c5_in_state>, 
<&clkreq_c5_bi_dir_state>;

                 nvidia,max-speed = <4>;
                 nvidia,bar0-size = <0x100000>;  /* 1 MB */
                 nvidia,device-id = /bits/ 16 <0x1AD4>;
                 nvidia,controller-id = <&bpmp 0x5>;
                 num-lanes = <8>;
                 nvidia,tsa-config = <0x0200b004>;
                 nvidia,aux-clk-freq = <0x13>;
                 nvidia,aspm-cmrt = <0x3C>;
                 nvidia,aspm-pwr-on-t = <0x14>;
                 nvidia,aspm-l0s-entrance-latency = <0x3>;
                 nvidia,aspm-l1-entrance-latency = <0x5>;

                 nvidia,host1x = <&host1x>;

                 num-ib-windows = <2>;
                 num-ob-windows = <8>;

                 nvidia,margin-port-cap = <0x194>;
                 nvidia,margin-lane-cntrl = <0x198>;
                 nvidia,cfg-link-cap-l1sub = <0x1c4>;
                 nvidia,event-cntr-ctrl = <0x1d8>;
                 nvidia,event-cntr-data = <0x1dc>;

                 nvidia,dvfs-tbl = < 204000000 204000000 204000000  
408000000
                                                         204000000 
204000000 408000000  666000000
                                                         204000000 
408000000 666000000  1066000000
                                                         408000000 
666000000 1066000000 2133000000 >;

                 iommus = <&smmu TEGRA_SID_PCIE5>;
dma-coherent;
                 iommu-map = <0x0 &smmu TEGRA_SID_PCIE5 0x1000>;
                 iommu-map-mask = <0x0>;

#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R>,
                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W>;
                 interconnect-names = "dma-mem", "dma-mem";
#endif

                 nvidia,bpmp = <&bpmp 5>;
                 nvidia,aspm-cmrt-us = <60>;
                 nvidia,aspm-pwr-on-t-us = <20>;
                 nvidia,aspm-l0s-entrance-latency-us = <3>;
};


Kind regards,

Martin