[RFC PATCH 0/3] arm64: errata: Disable FWB on parts with non-ARM interconnects

[Ard Biesheuvel]

On Thu, 16 Feb 2023 at 19:23, James Morse <james.morse at arm.com> wrote:
>
> Hello!
>
> When stage1 translation is disabled, the SCTRL_E1.I bit controls the
> attributes used for instruction fetch, one of the options results in a
> non-cacheable access. A whole host of CPUs missed the FWB override
> in this case, meaning a KVM guest could fetch stale/junk data instead of
> instructions.
>
> The workaround is to disable FWB, and do the required cache maintenance
> instead.
>

So the system should behave as if SCTLR_EL1.I==1 when FWB is enabled,
but it doesn't, right? Couldn't we just force SCTLR_EL1.I to 1 when
FWB is enabled? I.e., trap writes and override the I bit - and if we
want to pretend it is 0 we could trap reads and lie to the guest as
well, but I doubt we'd even need that.